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VHDL - not able to get an output

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startingvhdl

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I am in need of real help at the moment, i have UART system, the receiver, transmitter, clock divider are working fine with me.

i have to build up a decoder, that will translate the codes received from the PC using the hyperterminal software.

for example, if i press the "<" symbol on the PC Keyboard, the ALTERA FPGA - will receive the equivalent ASCII ( binary ) in the receiver part, the receiver part will forward it to the decoder ( which is mentioned below ) and the decoder will translate it into a word and forward it to the transmitter and transmitter will transmit it to the PC/hyperterminal screen..

the clock divider will synchronize the receiver and transmitter with the baud rate.

i have made the finite state machine below and assigned the respective hex codes of each letter, for examples to translate "<" in to "LESS" word, the hex has been forwarded.

but when i try to run it on the ALTERA FPGA, the hyperterminal software displays nothing on the screen, its been 3 week, i have been working on these parts.

*its compiling without any errors.


Code:
--example:  

--a<= x"FE";
--same as
--a<= "11111110";

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ASCII is 

PORT (getfromreceiver: in std_logic_vector(7 downto 0); -- receiver sends the 8bits of ascii BINARY
		clk : in std_logic;
		clr:	in std_logic;
		sendtotransmitter: out std_logic_vector(7 downto 0); -- translate word by word to the transmitter
		dready_receiver: in std_logic;
		dready_transmitter: out std_logic
			);
			
END ENTITY ASCII;

architecture design of ASCII is

	signal datain: std_logic_vector(7 downto 0);
		signal reg: std_logic_vector(7 downto 0);

type possiblestates is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9);
signal next_state: possiblestates;

BEGIN 
FSM: process(clk,clr,getfromreceiver)

--variable datain: std_logic_vector(7 downto 0):= (others => '0');
BEGIN -- S0 is the default state which will remains in the Non-valid char as long as no match occurs

		if (clr = '1') then 
			datain <= (others =>'0');
		elsif(clk'event and clk='1') then 
				if dready_receiver ='0' then
					datain <= getfromreceiver;
						if (datain = x"3C") then -- less sign
						next_state <= S1;
						elsif (datain = x"3D") then -- equal sign
						next_state <= S2;
						elsif (datain = x"3E") then --greater sign
						next_state <= S3;
						elsif (datain = x"26") then -- And symbol
						next_state <= S4;
						elsif (datain = x"7C") then -- OR symbol
						next_state <= S5;
						elsif (datain = x"2B") then --addition
						next_state <= S6;
						elsif (datain = x"2D") then --subtraction
						next_state <= S7;
						elsif (datain = x"2A") then --multiplication
						next_state <= S8;
						elsif (datain = x"2F") then --division
						next_state <= S9;
						else
						next_state <= S0; --"Non-valid char"
					end if;
			end if;
		end if;
end process;

OUTPUT: process(clr,next_state)
begin

	if(clr='1') then
	reg <= (others => '0');
	elsif (clk'event and clk='1') then
			--dready_transmitter <= '0';  -- the transmitter is detecting the falling edge signal 
			case next_state is 
						--LESS
						when S1 => reg <=x"4C"; 
						reg <=x"65"; 
						reg<=x"73"; 
						reg<=x"73"; 
						reg<=x"0D";
						reg<=x"0A";
						
						--EQUAL 
						when S2 => reg <=x"45"; 
						reg <=x"71"; 
						reg<=x"75"; 
						reg<=x"61"; 
						reg<=x"6C";
						reg<=x"0D";
						reg<=x"0A";
						--GREATER 
						when S3 => reg <=x"47"; 
						reg <=x"72"; 
						reg<=x"65"; 
						reg<=x"61"; 
						reg<=x"74";
						reg<=x"65";
						reg<=x"72";
						reg<=x"0D";
						reg<=x"0A";
						--AND 
						when S4 => reg <=x"41"; 
						reg <=x"6E"; 
						reg<=x"64"; 
						reg<=x"0D";
						reg<=x"0A";
						--OR 
						when S5 => reg <=x"4F"; 
						reg <=x"72"; 
						reg<=x"0D";
						reg<=x"0A";
						
						--Addition
						when S6 => reg <=x"41"; 
						reg <=x"64"; 
						reg<=x"64"; 
						reg<=x"69"; 
						reg<=x"74";
						reg<=x"69";
						reg<=x"6F";
						reg<=x"6E";
						reg<=x"0D";
						reg<=x"0A";
						
						--Subtraction
						when S7 => reg <=x"53"; 
						reg <=x"75"; 
						reg<=x"62"; 
						reg<=x"74"; 
						reg<=x"72";
						reg<=x"61";
						reg<=x"63";
						reg<=x"74";
						reg<=x"69";
						reg<=x"6F";
						reg<=x"6E";
						reg<=x"0D";
						reg<=x"0A";
						
						--Multiplication
						when S8 => reg <=x"4D"; 
						reg <=x"75"; 
						reg<=x"6C"; 
						reg<=x"74"; 
						reg<=x"69";
						reg<=x"70";
						reg<=x"6C";
						reg<=x"69"; 
						reg<=x"63"; 
						reg<=x"61";
						reg<=x"74";
						reg<=x"69";
						reg<=x"6F"; 
						reg<=x"6E"; 
						reg<=x"0D";
						reg<=x"0A";
						
						--Division
						when S9 => reg<=x"44"; 
						reg<=x"69"; 
						reg<=x"76";
						reg<=x"69";
						reg<=x"73";
						reg<=x"69";
						reg<=x"6F";
						reg<=x"6E";
						reg<=x"0D";
						reg<=x"0A";
						
						--Non-valid char
						when others => reg<=x"4E";
						reg<=x"6F";
						reg<=x"6E";
						reg<=x"2D";
						reg<=x"76";
						reg<=x"61";
						reg<=x"6C";
						reg<=x"69";
						reg<=x"64";
						reg<=x"20";
						reg<=x"43";
						reg<=x"68";
						reg<=x"61";
						reg<=x"72";
						reg<=x"0D";
						reg<=x"0A";
						
					end case;
				end if;
		
				dready_transmitter <= '1'; -- indicate with a HIGH to the transmitter that no byte will be sent
		end process;
		
		sendtotransmitter <= reg;
		
end design;
 

The below construct loads reg with x"0A". All other values are ignored. If you want to generate a character sequence, you need to step through the values with state machine. Furthermore, the sequence needs to be synchronized with the ready/busy state of the transmitting UART, a respective status input should be added to the decoder subdesign.
Code:
when S1 => reg <=x"4C"; 
reg <=x"65"; 
reg<=x"73"; 
reg<=x"73"; 
reg<=x"0D";
reg<=x"0A";
 

Just having a quick look at your code:
1. The asynchronous reset of your FSM process (if clr ='1') does not set 'next_state' (this is what I would expect from that reset).
2. The sensitivity list of the FSM process does not need the 'getfromreceiver' (besides the async reset, it is a clocked process).
3. The use of 'datain' in the FSM process is/seems wrong. Assigning 'datain <= getfromreceiver' means that the -next- clock cycle 'datain' will have the received value, and not 'this' clock cycle.
4. The sensitivity list of the OUTPUT process does not need the 'next_state', but needs 'clk' (besides the async reset, it is a clocked process).
5. 'Assigning' multiple values to the 'reg' in the OUTPUT process will -not- output all these values individually to 'reg'. Only one 'result' will end up in 'reg' (basically the last one). You need, for example, additional 'sub states' if you want to output a number of characters as a response to a single incoming character.

3 and 5 indicate that you do not yet understand some of the very important concepts about VHDL. I would go over the basics once again of how a clocked process works. I always think of it as a clocked registers (the "clk'event and clk='1'" indicate this). The data input of these clocked registers are a combination of AND/OR and other registers that is made up by everything after the "if clk'event and clk='1' then". In this case you have 'datain' and 'next_state' as clocked registers. When these registers are clocked, the data on their inputs already have to be present/stable. This means that when 'next_state' uses 'datain', it will be the 'datain' that was registered in a previous cycle.

Before running the code on a real world FPGA you should check your code using a test bench. This will show you that your code will not work as expected as it is now.
 

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