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[SOLVED] Need help with PFET gate biasing level in Li-ioin passive cell balancing.

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staple123

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Need help with PFET gate biasing level in Li-ion passive cell balancing.

Hi there,

Please take a look at a Li-ion balancing circuit, what gate biasing level should be chosen?

The question really is should the PFET be turned on in saturated region or triode region?

Thanks in advance.

PFET1.png
 
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If the balance control signal is either ON or OFF (the value of R1 controlling the balance) then PFET should be fully turned on (with no R3). You can not reliably control a transistors current by trying to provide a fixed bias to operate it in the saturation or triode region. You would need some form of negative feedback to do that.

If you want the PFET current level to be adjustable, then you need to generate an analog voltage (such as a averaged PWM signal) from the µP with feedback from the battery voltage to determine the proper balance voltage, and feed that to Q2's gate.
 

Thanks for your reply. This is on/off switch. You are correct, there is senor based feedback loop of the circuitry that feeds the uP, I didn't show.

My confusion is: Vds for PFet is only -3 V, if R3 is taken out, Vgs would be -9V, so PFET is then not in saturation. Since Vds is small, so should Vgs be reduced to a smaller value?

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I see Vgs larger the better. Thanks.
 
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With R3 removed you have two switch states:

If Q2 is off then the Vgs of Q1 is 0V (not -3V) so Q1 is off.

If Q2 if on then the Vgs of Q1 is -9V and it is fully on with a low drain-source resistance (Rds) and low Vds as determine by the transistor characteristics of the particular transistor you are using. It is not in the linear region.
 

Sorry I am editing this too many times,

When Control voltage is high: Q2 on, Q1 on.

for Q1: Vgs=-9V, Vds<-3V. My understanding is that for Pfet in saturation, abs(Vds)>abs(Vgs-Vth), assuming Vth=-4V, is this correct? I admit this is getting a little confusion for me.

Thanks for your patience..
 
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staple123 said:
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When Control voltage is high: Q2 on, Q1 on.

for Q1: Vgs=-9V, Vds<-3V. My understanding is that for Pfet in saturation, abs(Vds)>abs(Vgs-Vth), assuming Vth=-4V, is this correct? I admit this is getting a little confusion for me.
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That is true but you are still talking about the transistor as if it is operating in the linear/saturation region. The transistor is fully on with the operating point being very near the origin on the characteristic curve graph. At that point the Vds is determined by the Rds(on) (from the transistor data sheet), and the current through Q1, as determined by the value of R1 (it's acting as a switch with Vds likely less than 1V).
 

This is my original question, given small Vds, should I reduce Vgs to place Q1 in saturation region or use a large Vgs (taking out R3) to place Q1 in linear region? Which gives lower Rdson?

My understanding is that: Rds is larger in Saturation region than in linear region. So R3 should be taken out in order to have a small Rds for Q1. Even though Q1 is used as a switch, it is intentionally biased NOT as an on/off switch in saturation/off region, but is biased in linear region. Am I correct? This is really counter-intuitive to me.

Thanks for your help.
 

It should be biased as a switch, thus you want Vgs to be -9V (or greater) when the transistor is on. The higher the magnitude of Vgs (within its maximum rating) the lower the Rdson resistance and the better it acts as a switch.
 

Thanks, I really appreciate your help.

I still wonder under what applications, fets are biased in saturation, as current sources or as large loads?
 

staple123 said:
Thanks, I really appreciate your help.

I still wonder under what applications, fets are biased in saturation, as current sources or as large loads?
Click to expand...
If you use the transistor to vary the current flow and it's not be used as a switch, then it is operated in the saturation or triode region. This includes many types of linear circuits, such as linear current regulators, linear amplifiers (current or voltage, AC or DC), active load banks, etc.
 

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