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Help me with my Verilog code that concatenate data bits

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Bartart

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need help with verilog

hola!


this is my code, as you can see my job is to concate the partial data bits

XXX1XXXX where x is data from cntDataIn

MCirqMask[7:5] <= cntDataIn[7:5];
MCirqMask[3:0] <= cntDataIn[3:0];
MCirqMask[4] <= 1;

is there any easyiest way to do this?

thanks, Bart
 

need help with verilog

Hello
you can just write as
MCirqMask <= {cntDataIn[7:5], 1'b1, cntDataIn[3:0]};



Thanx and Regards
Dinnu
 

Re: need help with verilog

The easiest way would be, in that case:

MCirqMask <= cntDataIn | 8'b00010000;
 

Re: need help with verilog

Big Boy said:
The easiest way would be, in that case:

MCirqMask <= cntDataIn | 8'b00010000;
Click to expand...

may be this is the easiest way .. but at an extra area of 8 OR gates aprroximately 40 transisitros extra :)
 

Re: need help with verilog

If this is translated as a LUT or discrete OR, indeed!

But many of today's synthesizers will be able to translate OR gates, with constant inputs, to simple logic (x or 0 will turn to simply x, and x or 1 will turn so a single internal Vcc).

So, this could be a simple way to test your synthesizer :) Looking at the generated RTL code.
 

need help with verilog

This is not a big issue. I agree to the point of dinnu:

MCirqMask <= {cntDataIn[7:5], 1'b1, cntDataIn[3:0]};

This is the basic way of verilog to concentrate multiple data in a single data.
 

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