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QUERY REARDING INPUTS FOR STATIC TIMING ANALYSIS

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au_sun

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Hi,
I have some basic doubts regarding preparing input information for STATIC TIMING ANALYSIS,
1. HOW TO CALCULATE THE SETUP AND HOLD TIME FOR DESIGN ,
2. TO FIX THOSE SETUP AND HOLD TIME SHOULD I USE DATAS FROM THE LIBRARY .
3. HOW TO CALCULATE THE RISE TIME AND FALL TIME VALUES FOR THE CLOCK SIGNAL
4. HOW TO CALCULATE THE CLOCK LATENCY FOR THE CLOCK SIGNAL
5. HOW TO CALCULATE THE RISE TIME AND FALL TIME VALUES FOR THE input signals,


IF THERE IS ANY MATERIAL OR LINK PLS POST IT

THANX IN ADVANCE
 

1. setup and hold times are for flops not for design.. u need not calculate it. the fab will caluclate and u have to ensure that these timings are not violated in your design.

2.to fix setup/hold violations redesign your logic...
try to reduce the combinational path delay , wire delay , parasitics etc..

3,5. rise and fall time are calculated by the source/load capacitance ..

4. clock latency is the latency when the clock enters the block .. this is due to path delay/clock tree delay etc..
 

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