giovannigelli
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Hello,
I'm working as analog designer engineer. For the first time, I'm involved into the design of voltage regulators intended for applications with submicron cmos memories operating at 1.5, 1.8 e 2.5V.
My question concern the constraints, from a design point of view, that must be applied to the vdd of the memory systems (FLASH + control logic) so as to avoid improper operation of these apparatus (such as erratic reading/writing/erasing) and/or their damage.
In this respect, I would like to know:
- the max limits of variation tolerated, at application level, on the vdd of these systems, whatever the operating condition, including electrical transients having duration >500n- 1usec;
- if, for vdd spikes <500nsec (close to 100nsec) the above limit could be even larger and if so, how much.
- finally, what is the more frequent VCC-to-vdd dropout of use of these types of regulators in these systems
Many thanks in advance. Giovanni
I'm working as analog designer engineer. For the first time, I'm involved into the design of voltage regulators intended for applications with submicron cmos memories operating at 1.5, 1.8 e 2.5V.
My question concern the constraints, from a design point of view, that must be applied to the vdd of the memory systems (FLASH + control logic) so as to avoid improper operation of these apparatus (such as erratic reading/writing/erasing) and/or their damage.
In this respect, I would like to know:
- the max limits of variation tolerated, at application level, on the vdd of these systems, whatever the operating condition, including electrical transients having duration >500n- 1usec;
- if, for vdd spikes <500nsec (close to 100nsec) the above limit could be even larger and if so, how much.
- finally, what is the more frequent VCC-to-vdd dropout of use of these types of regulators in these systems
Many thanks in advance. Giovanni