Warning during Back annotation

Hi all:

I am using Cadence SOC Encounter to extract the post-layout netlist and SDF file. I wrote a testbench in verilog and I added the sdf_annotate command with itput arguments as my SDF file and my top-level instance name. Then during elaboration using the following command in NC-Sim::

ncelab -work worklib -cdslib /home/achundur/multiplier/post_sync/pnr/post_layout/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status worklib.mul_t:module

I am getting hundreds of warnings

assign ENCLK = net2333 ;
|
ncelab: *W,SDFNCAP (./mul_postlayout.v,32828|8): The interconnect source mul_t.mul_1.pp3reg_2.clk_gate_oup_reg.main_gate.Z is separated by a unidirectional continuous assign from the destination mul_t.mul_1.pp3reg_2.\oup_reg[56] .CP. The port annotation will still occur.

Can anyone please help in understanding what this is..
Please let me know, If I need to provide more description about the problem.

Thanks for any help.
Anil

This is normal. Dont worry about it for now. Check the result of the simulation. If it is correct, ignore the warnings.