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I would start from here: **broken link removed** . MIG is available in Xilinx Core Generator tool, which generates Verilog or VHDL code for DDR3 memory controller.
I would start from here: **broken link removed** . MIG is available in Xilinx Core Generator tool, which generates Verilog or VHDL code for DDR3 memory controller.
I want to write a data to ddr memory using multi port memory controller. Mibrobalaze and my custom core will write and read to ddr3 ram additinally my custom core will read and writ to ddr3 ram. But i coulnd find any documentation how to control multi port memory controller (mpmc) with my custom core ??? There is signals which names are below;
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