I'm new to Verilog, cant get what I have to compile in

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module top(most, least, key0, key1, key2, lights);
 
input [2:0] most;
input [2:0] least;
input key0, key1, key2;
output [1:14] lights;
wire [5:0] result;
wire [3:0] ones;
wire [3:0] tens;
 
    if(key0==1)
    begin
        adder add0(most, least, result);
    end
    else if(key1==1)
    begin
        subtractor sub0(most, least, result);
    end
    else if(key2==1)
    begin
        mulitplier mult0(most, least, result);
    end
    else
    begin
        seg7 dip0(most,lights[1:7]);
        seg7 dip1(least,lights[8:14]);
    end
    
    if(result>9)
    begin
        binary_to_BCD(result,ones,tens);
        seg7 dip2(tens, lights[1:7]);
        seg7 dip3(ones, lights[8:14]);
    end
    else    
    begin
        seg7 dip4(result, lights[8:14]);
    end
 
endmodule
 
 
 
//Subtracts numbers when msb>lsb
module subtractor(Z, W, SUB);
    input [2:0] Z;
    input [2:0] W;
    output reg [3:0] SUB;
    
    always@(Z,W)
        if (Z >= W)
        begin
            assign  SUB = Z - W;
        end 
 
endmodule
 
 
//Adds numbers
module adder(Q, R, S);
    input [2:0] Q;
    input [2:0] R;
    output reg [3:0] S;
    
    always@(Q,R)
        assign S = Q + R;
 
endmodule
 
 
//Multilies numbers
module mulitplier(T, U, M);
    input [2:0] T;
    input [2:0] U;
    output  [5:0] M;
    
    assign M = T * U;
 
endmodule 
 
 
//7_segment decoder
module seg7(bcd,leds);
    input [3:0]bcd;
    output reg [1:7] leds;
 
    always@(bcd)
        case(bcd) //abcdefg
            0: leds = 7'b1111110;
            1: leds = 7'b0110000;
            2: leds = 7'b1101101;
            3:  leds = 7'b1111001;
            4:  leds = 7'b0110011;
            5:  leds = 7'b1011011;
            6:  leds = 7'b1011111;
            7:  leds = 7'b1110000;
            8:  leds = 7'b1111111;
            9:  leds = 7'b1111011;
            default:    leds = 7'b0000000;
        endcase
    
endmodule
 
 
//converts from binary to bcd for numbers >9
module binary_to_BCD(A,ones,tens);//c1,c2,c3,c4,d1,d2,d3,d4);
    input [5:0] A;
    output [3:0] ones, tens;
    wire [3:0] c1,c2,c3,c4;
    wire [3:0] d1,d2,d3,d4;
    
    assign d1 = {1'b0,A[5:3]};
    assign d2 = {c1[2:0],A[2]};
    assign d3 = {c2[2:0],A[1]};
    add3 m1(d1,c1);
    add3 m2(d2,c2);
    add3 m3(d3,c3);
    assign one = {c3[2:0],A[0]};
    assign tens = {1'b0,c1[3],c2[3],c3[3]};
 
endmodule
 
//assigns binary a bcd
module add3(in,out);
input [3:0] in;
output [3:0] out;
reg [3:0] out;
always @ (in)
        case (in)
        4'b0000: out <= 4'b0000;
        4'b0001: out <= 4'b0001;
        4'b0010: out <= 4'b0010;
        4'b0011: out <= 4'b0011;
        4'b0100: out <= 4'b0100;
        4'b0101: out <= 4'b1000;
        4'b0110: out <= 4'b1001;
        4'b0111: out <= 4'b1010;
        4'b1000: out <= 4'b1011;
        4'b1001: out <= 4'b1100;
        default: out <= 4'b0000;
        endcase
endmodule