veena15
Newbie level 1
HI
The primitive tranif0 and tranif1 are not support by Xilinx for synthesable design ,but my design needed to implement the function of primitive "tranif0 or tranif1 "
for example if C is 1 , A <=>B(bidirectional transfer ) , else C is 0
thank you !
The primitive tranif0 and tranif1 are not support by Xilinx for synthesable design ,but my design needed to implement the function of primitive "tranif0 or tranif1 "
for example if C is 1 , A <=>B(bidirectional transfer ) , else C is 0
thank you !