break down voltage between drain and body

Can any body give me some examples of the break down voltage between drain and source in any CMOS process?
Thanks in advance!

At very large reverse bias of PN diode , beyond the peak inverse voltage or PIV, a process called reverse breakdown occurs that causes a large increase in current (i.e., a large number of electrons and holes are created at, and move away from the p–n junction) that usually damages the device permanently. Now If applied voltage between drain and body of MOSFET is higher than its breakdown voltage, breakdown of reversed biased drain-body diode can take place. But this doesn't happens for source and drain because they don't form a diode. At normal operating voltages, breakdown can't occur. What do you mean by example.?

yadavvlsi said:

At very large reverse bias of PN diode , beyond the peak inverse voltage or PIV, a process called reverse breakdown occurs that causes a large increase in current (i.e., a large number of electrons and holes are created at, and move away from the p–n junction) that usually damages the device permanently. Now If applied voltage between drain and body of MOSFET is higher than its breakdown voltage, breakdown of reversed biased drain-body diode can take place. But this doesn't happens for source and drain because they don't form a diode. At normal operating voltages, breakdown can't occur. What do you mean by example.?

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Hi yadavvlsi,
Thanks for your reply! i understand it does not occur in normal operating condition. But in CMOS RF VCO design, the transistors are potentially stressed. That is why I want to know the breakdown voltage between drain and body.

As you mention, in RF VCO transistors are potentially stressed. So you have to simulate to get the breakdown voltage.

liusupeng said:

Can any body give me some examples of the break down voltage between drain and source in any CMOS process?

Click to expand...

Depends on the process used, and should be mentioned in the PDK doc.

You should not count on any simulated breakdown even
being there, certainly not its parametric details.

D-B breakdown is going to be modulated by the gate in
a vector sum near the D-B-G area. The reliability aspect
of concern is hot carrier stressing of the gate and spacer
oxides, which will drift device attributes and degrade the
oxides over the longer term. Now these are ameliorated
at high temp and reversing conditions (like HF/RF), and
very dependent on the details of the stress environment,
so again a circuit model is unlikely to be useful other than
in showing what the electrical stress is.

D-S breakdown can be lower than D-B if the channel length
is short. It's likely to be less abrupt / have a sloppier "knee".

Now breaking down or going forward bias will inject stuff
into the substrate that can end up tickling unexpected
places in the nearby layout (nearby being whatever the
diffusion length is, absent ties and junctions to remove
the minority carriers).

If you know the well doping and assume the S/D are a
whole lot higher, you can find breakdown voltage charts.
These would be a best-case, with corners and field plates
(such as gate) worsening the value from there.

A few minutes on a parameter analyzer / curve tracer
is much more to-the-point. If you have none, foundry
applications-support people might already have the
data for some close-enough geometry.

For a 5V process, the drain/source breakdown voltage might be 10V.