[SOLVED] ReRAM design with vhdl or matlab

Hi All,

I wanna describe the behavioral model of resistive ram, i have done some work but i m not sure cos since it is a very new technology it is difficult to find some reference design, it would be really great if you know how to do it in vhdl or matlab.

VHDL is a hardware description language - it describes the RTL level of a digital circuit.
It has nothing to do with the silicon process itself...

Thank you for your reply. Yes sure i know already it is hardware description language, but we can model the memories with vhdl which consists of write and read operations.i wanna model the behavioral model, i found some vhdl model for sram and dram, so can i use the same model that introduced for sram? cos all the pins are the same just write and read time is different then SRAM.

You would need to find a data sheet for a particular resistive ram, and follow the timing diagrams. But should be possible. With large memories, it can be useful to use access types inside protected types to prevent huge memory usage inside a simulator, assuming you are only going to populate it sparsly.

Actually this resistive ram does not have a data sheet cos i created it's spice model and measured read and write access times. So i know only these parameters. Do you think these are enough to create behavioral model in vhdl?

aibar,

Is it an "of the shelf" memory or only a theoretically conceived model?

Hi shaiko
This model just created based on previous works and heuristic methods, it is not a off the shelf memory yet, since i got reasonable wirte and read times from spice model , i wanna create rtl level design and see the memory behaviour in a embedded application, then i will try to improve it based on it's behaviour. I think i just need to create a regular ram model which is just reading and writing but i have to insert some delay for write operation cos as you know non-volatile memories has long write time. Do you think is it reasonable?

It sounds about right...but the timing analysis is the thing you should work on.
The HDL behavioral model of a synchoronous RAM is VERY simple - and again, it has nothing to do with the silicon process.

Is a simple VHDL code for a RAM matrix is what you're looking for ?

yes as you said there is nothing to do with silicon process, since i wanna just see memory behaviours with the delays in an embedded application i wanna create rtl level, so i thought i can use a simle code for ram, i already have it there are so many vhdl code for ram in the internet, but i m not sure about using this one, cos there are two points;
-if i compare rram to sram; rram has long write time.
-sram is volatile, rram is nonvolatile.
so by considering these two features, i am thinking that, i can use the same vhdl code that i use as sram by introducing some delay which i have got from my measurements for write operation, read operation has the same delay as sram already.

surely i know it has nothing to do with silicon, my point is to just simulate to see how much does this delay(for write process) effect the performance of embedded processors, from this point of view i can see that is it applicable or not;

for example this sram code is given, i guess i can use the same model with the delay before write operation

-- a simple 4*4 RAM module (ESD book Chapter 5)
-- KEYWORD: array, concurrent processes, generic, conv_integer--------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------
entity SRAM is
generic(
width:integer:=4;
depth:integer:=4;
addr:integer:=2
);
port(
Clock:in std_logic;
Enable:in std_logic;
Read:in std_logic;
Write:in std_logic;
Read_Addr:in std_logic_vector(addr-1 downto 0);
Write_Addr: in std_logic_vector(addr-1 downto 0);
Data_in: in std_logic_vector(width-1 downto 0);
Data_out: out std_logic_vector(width-1 downto 0)
);
end SRAM;
--------------------------------------------------------------
architecture behav of SRAM is

-- use array to define the bunch of internal temparary signals

type ram_type is array (0 to depth-1) of std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;

begin
-- Read Functional Section
process(Clock, Read)begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;

-- Write Functional Section

process(Clock, Write)
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Write='1' then
tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
end if;
end if;
end process;
end behav;

This is a synchronous model. Therefore, you should NOT add any extra "delays", unless they are relative to the clock. That would go against the whole idea of having it synchronous in the fuirst place!

Also, as "Read" and "Write" are evaluated under the clocks edge - it's redundant to have them in the sensetivity lists.
A synchronous process should be sensitive only to the "clock" and to an asynchronous "set" or "reset" signals (if available).

---------- Post added at 11:13 ---------- Previous post was at 10:58 ----------

One more thing. TrickyDicky will correct me if I'm wrong - but in my designs I never "high Z" the outputs of the read port when "Read" is '0'.
Why should you allow a floating logic value to be strobed out at anytime ?
Why shouldn't the read port always be driven by Data_out(address) ?

Unlike a write action - a read action is transparent to the memory matrix itself.
It's a signal for the memory controller (FIFO , LIFO , etc...)

yes i m agree with you about sensitivity list and floating date allowing, this was just a sample code in the internet there are so many rooms to be corrected, i think it is more clear now, i guess i can just sencronize it with the clock, since read operation does not take more then one clock cycle i can read anytime, but for write operation i can simply synchronize access time with my clock frequency i think it would be the easiest and reliable way, and also some control signals to avoid burs addressing and so on. Thank you for your suggestions guys, they were really useful