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automatic generation of bit-true model with timing info in Simulink

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rogeret

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hi,
In Matlab 2011, it is allowed to use simulink to creat HDL code for a system. When test vector is too much, given it being too slow to do a bit-true verification through HDL code , is it available to automatically create a corresponding c , m , sc or sv code which can model the timing info and parallel architecture? Or any example?
Thanks!
 

I'm not sure I understand your question. Specifically, can you elaborate on this:
When test vector is too much, given it being too slow to do a bit-true verification through HDL code
Click to expand...
Are you trying to create a testbench, or what?

Have you looked at SysGen?
 

Yes, I am trying to create a testbench. I hope this testbench can do bit-true verification(to compare with fixed point system-level arithmetic code bit by bit) and it is not written in HDL because the verification will cost much time when test vector is too much. Can Matlab Simulink help me to do this automatically?
I dont know about SysGen. Could u tell me what does it do for u in everyday work?
thanks!
 

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