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gate count estimate of FSK reciever on FPGA

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warriorwithin

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I want to implement a FSK reciever on an FPGA for 4 channels in (600-2k) hz range. The FPGA has a maximum gate count of about 300k.
Would the area be enough to implement this.

Are there any rules of thumb regarding an FSK reciever and gate count?
 

It will depend mostly on how you implement it. A 300k logic element device sounds like you have a large device. I would implement it and then see how the logic usage stacks up.
 

I have no idea as to how much the different demodulation schemes fare when it comes to area.
choices are
a)envelope detection
b) zero crossing

Anybody have Idea of comparitive areas of these two modulation schemes?
 

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