Buriedcode
Full Member level 6
Hi,
I'm sure many have asked this before, but I searched the board and could not find an answer. I have a number of graphic LCD displays, 240x128 to 320x240, mostly monochrome, and a couple of colour ones (CSTN). Whilst I have a few epson controller's, as well as a SSD1906 which can drive almost any display I have, I wanted to see if I could make a smaller, simple controller using a CPLD.
To start off with, I'm trying to get my CSTN display up and running, just generating timing signals with the data input fixed (all 1's or all 0's, as in all pixels on, or all pixels off). After that I can work on colour pallettes, and a memory interface for the frame buffer. Believe it or not I am confident that I can get the memory interface working, and have already 'simulated' a design for converting 8bpp to the format required by the colour STM display.
My problem is the timing. Here's the display:
**broken link removed**
I have gone over that timing diagram (page 12) as well as the timing specs many many times, but I'm still unable to get anything on the display. Contrast is set at thew recommended 2.0V, and when I disconnect the clock lines (FLM, CL1, CL2) it puts up random lines - which means the contrast is fine. So obviously I'm doing somthing wrong with the timing. Here's what I've been doing:
input clock / 8 -> CL2.
CL2 drives a counter, for the input data, which counts from 0, to 119 (120 input data).
When this counter reaches 119, CL1 is pulsed high for a period of CL2. (this is the line pulse)
One again, CL1 drives another counter, 0-239, for 240 lines (this is the FLM - first line marker).
When the counter is 0, FLM is high.
That does nothing for the display. So I added a delay between the last byte written on a line, and the next line. So after CL1 is high (start of line), I send out 120 clocks to read in pixel data, then wait a further 8 CL2 periods before starting a new line.
This is getting me down as I'm stuck on the first hurdle - generating timing.
I started with this idea: fpga4fun.com - Graphic LCD panel Used the verilog code, and it produced the waveform as expected, except I changed the numbers so its 120 horizonal pulses, and 240 lines (instead of 320 lines) and that didn't help.
If anyone has any form of verilog/VHDL or schematic form of a timing generator for this LCD I would be grateful, as I'm tearing myhair out, thinking its something else, like a hardware fault.
Any advice is welcome, thanks!
Buriedcode
I'm sure many have asked this before, but I searched the board and could not find an answer. I have a number of graphic LCD displays, 240x128 to 320x240, mostly monochrome, and a couple of colour ones (CSTN). Whilst I have a few epson controller's, as well as a SSD1906 which can drive almost any display I have, I wanted to see if I could make a smaller, simple controller using a CPLD.
To start off with, I'm trying to get my CSTN display up and running, just generating timing signals with the data input fixed (all 1's or all 0's, as in all pixels on, or all pixels off). After that I can work on colour pallettes, and a memory interface for the frame buffer. Believe it or not I am confident that I can get the memory interface working, and have already 'simulated' a design for converting 8bpp to the format required by the colour STM display.
My problem is the timing. Here's the display:
**broken link removed**
I have gone over that timing diagram (page 12) as well as the timing specs many many times, but I'm still unable to get anything on the display. Contrast is set at thew recommended 2.0V, and when I disconnect the clock lines (FLM, CL1, CL2) it puts up random lines - which means the contrast is fine. So obviously I'm doing somthing wrong with the timing. Here's what I've been doing:
input clock / 8 -> CL2.
CL2 drives a counter, for the input data, which counts from 0, to 119 (120 input data).
When this counter reaches 119, CL1 is pulsed high for a period of CL2. (this is the line pulse)
One again, CL1 drives another counter, 0-239, for 240 lines (this is the FLM - first line marker).
When the counter is 0, FLM is high.
That does nothing for the display. So I added a delay between the last byte written on a line, and the next line. So after CL1 is high (start of line), I send out 120 clocks to read in pixel data, then wait a further 8 CL2 periods before starting a new line.
This is getting me down as I'm stuck on the first hurdle - generating timing.
I started with this idea: fpga4fun.com - Graphic LCD panel Used the verilog code, and it produced the waveform as expected, except I changed the numbers so its 120 horizonal pulses, and 240 lines (instead of 320 lines) and that didn't help.
If anyone has any form of verilog/VHDL or schematic form of a timing generator for this LCD I would be grateful, as I'm tearing myhair out, thinking its something else, like a hardware fault.
Any advice is welcome, thanks!
Buriedcode
