vco design corner analysis CADENCE

Hi all

Brief Overview:-

I am designing an LC VCO at 2.5GHz(cross coupled NMOS pair) in UMC 18 process with 5 bit binary weighted switched capacitor ckt for reducing KVCO.
Pls note that this VCO is going to be a part of a PLL so i wont have the access to the control voltage of the varactor.
I am using Cadence.

Problem:-

In typical analysis I am getting the tuning from 2.38GHz to 2.64GHz . While doing corner analysis for the worst case, the center frequency ( which ideally should be 2.5GHz) gets shifted to a frequency beyond the tuning range which cant be brought to the desired central frequency of oscillation which is 2.5GHz (by changing the external bits to the switch capacitor bank).

I can vary only 3 params 1. the varactor size 2. the switch capacitors (with external inputs like b0b1b2b3b4) and 3. a fixed capacitor in parallel with the switch capacitors.... The problem is after fabricating the PLL chip I wont have access to any of these 3 as we have decided to go for full on chip design....

Can someone give an idea how to go for changing the parameter such that the central frequency comes back to 2.5GHz.


What I ve tried is :-

Varying the varactor size to increase the tuning range but its of no use, as again the frequency goes beyond the tuning range in worst case corner and doesnt becomes 2.5GHz (by changing the external bits to switch capacitor)

Regards

I think your cap bank between 0 & 31 simply must cover the full PVT range, with a value for typ. cond. somewhere in between.

Of course your fine tuning accuracy (frequency resolution) will suffer from such an extended range, if you can't spend a 6^th bit.