xiongdh
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data memory protection?
Can someone give me any advice about how to design a data memory protection algorithm for embedded ram in a smart CPU card.
the function of the data memory protection can described like the followed:
"Any access to RAM by the CPU is interfaced by a special protection mechanism . Designed as security feature, this interface scrambles address and data lines in order to decorrelate the physical location and the logical address of
all data stored.
Hence, data located at contiguous addresses are spread
over the entire physical RAM matrix, where at the same
time the individual data stored at each address is
scrambled as well. This prevents bytes stored at e.g. two
consecutive addresses from being stored at two physical
consecutive locations.
Controlled by two Special Function Registers called
DMPTL and DMPTH, the mapping between logical and
physical locations can be varied, as the 16-bit contents of
these two registers become part of the scramble
mechanism used for the data stored. Any new value
written into DMPTL or DMPTH will result in a different
mapping between logical and physical locations of the
entire RAM. A value of 00h in both registers, which
represents also their reset value, will directly connect the
RAM to the CPU and thus deactivate the
protection mechanism."
Can someone give me some article about this topic? thank you all.
Can someone give me any advice about how to design a data memory protection algorithm for embedded ram in a smart CPU card.
the function of the data memory protection can described like the followed:
"Any access to RAM by the CPU is interfaced by a special protection mechanism . Designed as security feature, this interface scrambles address and data lines in order to decorrelate the physical location and the logical address of
all data stored.
Hence, data located at contiguous addresses are spread
over the entire physical RAM matrix, where at the same
time the individual data stored at each address is
scrambled as well. This prevents bytes stored at e.g. two
consecutive addresses from being stored at two physical
consecutive locations.
Controlled by two Special Function Registers called
DMPTL and DMPTH, the mapping between logical and
physical locations can be varied, as the 16-bit contents of
these two registers become part of the scramble
mechanism used for the data stored. Any new value
written into DMPTL or DMPTH will result in a different
mapping between logical and physical locations of the
entire RAM. A value of 00h in both registers, which
represents also their reset value, will directly connect the
RAM to the CPU and thus deactivate the
protection mechanism."
Can someone give me some article about this topic? thank you all.