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Xilinx System Generator Clock Signal

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Hello!

Hardwareimplementation works fine. My problem is the clock signal. I need the clocksignal in my design and don´t know how to get the signal. (Something like clockprobe). I tried a simple vhdl (with src_clk_1 and src_ce_1) file as blackbox - but it didn´t work. Is there any trick to use the clock signal?

best regards
 

Generate for HDL and pull it out of the code.

Why didn't the blackbox work? What do you need the clock signal for?
 

The clockout - blackbox works fine in hardware - but not in simulation. I need it for ADC clocking. Worst case I will connect it with the black box. But I´d like to know if there is any possibilty to get the clock signal in simulation.
 

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