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regarding setup and hold violation

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venkatramanan

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other than insertion deleting ,resizing ,and reducing operating freq,how we can reduce setup violations.interviewr told somemore than 8method is there for reducing setup violations. ple any body knows reply me.i have interview.ple
 

There are many other methods than sizing to fix setup violations.
1. Logic restructuring: Reduce combinational logic delay by minimising number of logic levels.
2. Vt swapping: Sweeping HVT by RVT or LVT. Standard cell library has three type of cells. HVT(High threshold voltage), RVT (Regular threshold voltage), LVT (Low threshold voltage). These have drive strength in increasing order starting from HVT > RVT > LVT.
3. Buffering: Put buffer if there is a long net in layout or a net have high fanout.
4. Pin swapping: Delay from input to output is different for different input to output arcs due to on time resistance of transistors in the cell.
5. You use skew to meet setup time. This concept is called useful skew.

If you have doubt related to any point, let me know I'll try explain that in a elaborate way.
 
thank u so much:) and having some doubt .1:in first point how to minimize the logic levels.were we go and minimize that one.2:pin swapping some wat confusing can u elaborate me :) ple
 

2. Pin Swapping will reduce the routing delay.
suppose a pin is Top most corner of the board and the logic driving the output presents at bottom, then there will be a set up violation
if the pin is placed nearby the logic, the routing will be eliminated.
 
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Logic level minimization is done by both synthesis tool and physical design tool automatically. You need to worry about it. You should know the concept. Consider a cell have two inputs(A and B) and output(Z), then cell delay from A > Z is different from cell delay from B > Z. This is related to on resistance of transistors. For this you need to see at circuit level.

**broken link removed**
**broken link removed**
**broken link removed**
Delay calculation - Wikipedia, the free encyclopedia
 

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thank u sir.logic minimization nothing but like kmap reduction .my understanding correct ah sir.if its wrong correct me

---------- Post added at 11:22 ---------- Previous post was at 11:15 ----------

another one doubt regarding useful skew.we are ly generating useful skew .how we are giving that one also.ple explain me sir
 

Logic restructuring is done during synthesis it uses at lot of complex algorithm to do optimization. Go through below link.
https://www.ida.liu.se/~petel/SysSyn/lect3.frm.pdf

Hold time equation
1. Tcq + Tcomb> Tskew + Thold
Setup time equation
2. Tcq + Tcomb< Tskew +T - Tsetup
If skew is positive it helps in setup but degrade hold and if skew is negative it helps hold but degrade setup.
 

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