FM demodulation - modulating signal up to 16 kHz

Hello everyone,

i don't have much experience in RF world but now i have to design some method of FM demodulation. Although i have read a few things on this topic, i still have some problems and would be really grateful for some help from somebody with bigger experience.

So...

I have this FM signal with parameters:

Carrier frequency: fc=100 kHz
Max. frequency deviation: Δf= ±20 kHz
Frequency of modulating signal: fm= from 0 Hz to 16 kHz

that i have to demodulate. In my project i can change freely carrier frequency fc in range, lets say: from 50 kHz even up to 2 MHz, but deviation and modulating signal i cannot change. I've chosen 100k, because lower frequencies seems less problematic to me (am i wrong?).
So, i have read about many different techniques of FM demodulation, there is plenty of them:
slope detector, foster seeley discriminator, ratio and quadrature detectors, PLL demodulator and even zero crossing or pulse counting method from some fancy '70 style radios. I have seen schematics including PLL on 4046 or LM565. I even found some neat ICs, for example ADVFC32, which is Frequency to Voltage Converter (FVC) working up to 100kHz: https://www.analog.com/static/imported-files/data_sheets/ADVFC32.pdf

But still have some concerns...
It's about frequencies of modulating signal up to 16 kHz. Im not talking about frequency deviation but about modulating signal frequency. If i understand FM well, it seems that frequencies of my FM signal changes from fc-Δf kHz to fc+Δf kHz.. up to 16000 times a second. Thats pretty much i quess. So i need dynamic enough demodulator. Unfortunately, in data sheets dynamic parameters (e.g. how fast frequency changes will still give properly demodulated output) are not often included

Many demodulators that i have found operate in lower frequencies, for example for speech and audio: 300 to 3000 Hz. It seems reasonable, because for example PLL can lose its lock when frequency change very rapidly.

So, i think what i need, is fast FM demodulator / fast FVC.

My question is: does there exists such fast FM demodulators? Can PLL, for example on 4046 can be fast enough to perform such demodulation? Or maybe on some other IC? Or would be it enough to just use this ADVFC32, after lowering fc to 80kHz? Some other simple FVC?

Im quite confused and tired. Could really use some help, tricks or tips. Any hints, really.

With regards,
Michael.

Hi Michael,

I think 4046 is adequate for demodulating your signal, and using high frequencies (as possible) for fc is usually better. If your Vcc = 10, you can let fc be up to about 1 MHz for 4046. The key part in a PLL demodulator (or for other functions) is the low pass filter between the phase comparator and VCO input. Also the frequency range set for the VCO affects, with the LPF, the loop response.

====================
Note:
For sinusoidal frequency modulation, the bandwidth required to transmit or receive the FM signal is:

BW = 2*(df + fm)
Where
df is the maximum frequency deviation
fm is the sinusoidal modulating frequency

Therefore in your project, BW = 72 KHz (+/- 36KHz at fc)
====================

Your project is a very good start to let you be interested in studying how to design a PLL circuit which is one of my favourites.

Kerim

If you use an IC to do the demodulation, make sure it is not a stereo receiver chip....since they do very wierd things above 15 KHz deviation rate.

If you plan on changing the carrier frequency, do you have a tracking local oscillator in the receiver, so that a constant IF frequency is sent to the demodulator? If so, you might choose 10.7 MHz as the IF frequency, and upconvert the received signal to there. There are plenty of 10.7 MHz FM demodulator chips/circuits that are designed for 10.7 MHz.

If you do not have a tracking LO reciever (superhetrodyne), how were you planning on retuning the discrimator resonant circuit for each new carrier frequency?

KerimF said:

The key part in a PLL demodulator (or for other functions) is the low pass filter between the phase comparator and VCO input. Also the frequency range set for the VCO affects, with the LPF, the loop response.

Your project is a very good start to let you be interested in studying how to design a PLL circuit which is one of my favourites.

Click to expand...

I must say, that of all these methods PLL seems most complicated to me. The general rule is simple and comprehensive, yes, but all the good mood is gone when we get to calculations. Do you happen to remember any books or tutorials where the designing issues are well covered and/or explained?

biff44 said:

If you plan on changing the carrier frequency, do you have a tracking local oscillator in the receiver, so that a constant IF frequency is sent to the demodulator? If so, you might choose 10.7 MHz as the IF frequency, and upconvert the received signal to there. There are plenty of 10.7 MHz FM demodulator chips/circuits that are designed for 10.7 MHz.

Click to expand...

So far i don't have any local oscillators. 10.7 MHz seems out of range, but it looks like 455 kHz is another popular IF. If i would like to shift it to IF, is 455 kHz much worse than 10.7 MHz?

biff44 said:

If you do not have a tracking LO reciever (superhetrodyne), how were you planning on retuning the discrimator resonant circuit for each new carrier frequency?

Click to expand...

Im not planning to change carrier frequency later. I can select any carrier frequency from 50kHz - 2000 kHz now, but once i make a decision, i won't be able to change it. If i would use resonant circuit it would have to be tuned only once. (btw. isn't the bandwidth too wide to use resonant circuit?)

KerimF said:

Note:
For sinusoidal frequency modulation, the bandwidth required to transmit or receive the FM signal is:

BW = 2*(df + fm)

Click to expand...

Yeah, co called Carson's rule of thumb

Hello Michael,

When I was young (29 :smile: ) I had two references:
The datasheet of CD4046
“Linear Applications Handbook” From National Semiconductor, Application Note 46, Thomas B. Mills, June 1971

Now it seems there are plenty of references and even free software for designing PLL.
I am afraid I can't help you since I have no idea about the level of your background.
Also what may look to me as complicated equations, they may look to you familiar based on your actual studies.

I was most interested in PLL when I designed and built (as an MS thesis) my simple AM demodulator for all modulation indexes, including the suppressed carrier case.
Its circuit is based on one conventional PPL as of 4046. Obviously its AM input signal (with or suppressed carrier) was chosen to have a carrier frequency of 455 KHz (the AM IF). The key point of its design was to restore properly the carrier (frequency and phase) in the worst case. That is when it is suppressed. This happened when I was 29. This year, I simulated it on LTspice and I was able to improve it just for fun.

Good luck,

Kerim

As KerimF said the bandwidth of your signal is 72KHz, using such a low IF as 100KHz, means that you can't use any resonant LC circuits or filters because they will lead to sideband shifts and cutting (reduction in amplitude) and hence distortion on the demodulated waveform.
Frank

Generally speaking, broadcast FM receivers (deviation+/- 75 KHz) demodulate at 10.7 MHz. Narrowband FM receivers (deviation 5KHz or less) demodulate at 455 Khz. If you want to demodulate a 100 Khz @ 20 Khz deviation signal, you'll have to heterodyne it up to a higher frequency.

KerimF said:

Now it seems there are plenty of references and even free software for designing PLL.

Click to expand...

The problem with references and software for PLL is that, most often they are meant to help design frequency synthesizers or dividers. I have no doubt the PLL is working great when it has to give steady frequency, but things are more complicated, when it has to deal with some dynamic behaviour.

chuckey said:

As KerimF said the bandwidth of your signal is 72KHz, using such a low IF as 100KHz, means that you can't use any resonant LC circuits or filters because they will lead to sideband shifts and cutting (reduction in amplitude) and hence distortion on the demodulated waveform.
Frank

Click to expand...

What about active (opamp) filters or the passive ones (R+C)?

By the way, it turned out, that deviation of the signal won't exceed 6 kHz, so also bandwidth will be lower. (yes, i know it seems strange that this quantity changes but... well it's complicated. beforehand the margin was overpredicted)

I did some additional research about FM demodulation. By this time the most appropriate methods seems to be either Quadrature Demodulator or PLL. Quadrature demod, because it's quite simple, straightforward and dynamic independent (mostly) or PLL because it requires no inductive elements to work and has linear output.

I have a question about Quadrature Demodulator:
it contains basically three elements: 1) phase shifter 2) mixer 3) low pass filter. Phase shifter has to change the phase of signal by 90 degrees for carrier, and more or less for other frequencies. So far i have seen, that changing phase is done using resonant circuits (RLC). As far as i know, there are also phase shifters build on opAmps, but they seem to work properly only for lower frequencies (circa 10 kHz?). So, the question is: is it possible to shift the phase of the signal (lets say, sinusoidal) in any other way than resonant circuit?

I have a question about PLL:
Now i am even able to name properly my concerns. It's the slewing rate of the signal. So, it seems intuitive, that if the signal changes too much rapidly, it is very possible that it will lose lock. So.. i have read the Roland E. Best book "Phase locked loops, design, simulation and applications" and have found there some handy looking equation:

dω/dt <= 0,5*(ω_n)^2

Which has the meaning: if rate of angular frequency change of ref signal is lower than the half the square of normal ang. frequency ω_n, then PLL should remain locked.
The question, very important question is: is it reasonable to count only on this condition when figuring out whether PLL will lose lock or won't? If my maximum slew rate of frequency is lower than 0,5*(ω_n)^2, can i be SURE, that PLL will demodulate such signal? Or are there any other conditions? (when being inside lock range, of course..)

I did some math: so my instanteous frequency of signal (modulation sinus) is f=fc + fd*sin(2*pi*fs*t), where:
f - freq of FM signal, fc - carrier, fd - deviation, fs - freq of modulating signal

so, SR (slew rate) is df/dt = 2*pi*fd*fs*cos(2*pi*fs*t)

and the max instanteous freq SR is: (df/dt)max = 2*pi*fd*fs (for cosine being 1)

and the value, for (max) fd=6 kHz and fs=16 kHz is (df/dt)max=602,88 MHz/s

So, if i fulfill the 0,5*(omega_n)^2 < 602,88 MHz/s condition then it means that PLL won't lose lock inside lock range?

Do these calculations make sense? Am i right or wrong?

Michael

Hi Michael,

If you have LTspice (a professional free simulator) it would be possible for me to share with you my work. And we could make the necessary changes to let the circuit work as an FM demodulator. It would be a basic circuit on which you can experiment any formula you may be interested in.

The answer of your question is related to the PLL topology, mainly to the type of its phase detector.

With LTspice, it is also possible studying the response of closed loop in the s domain. Then the circuit can be simulated in the time domain (transient analysis) by applying any signal to test its real time response (as lock, settling time and others).

I am getting old so I may not be able to walk with you in all details since the subject is rather out of my actual projects (controller designs) though communications was my favourite field in my high studies.

Kerim

Hi Kerim

It would be great if you could share with me some of your work. I have acquired LTspice, although i have not used it before. But i think it's not a problem, i can read some tutorials. If you would be so kind, i have PM'ed you my e-mail address.

I am not expecting of you, or anybody else walking with me on every tiny detail. Danger of unlocking PLL is just my main concern so i just wanted to be sure..

BY the way, i stumbled across quite handy textbook "Analog and digital filter design" by S. Winder, where is entire chapter concentrated on designing PLL loop filters. There is even exemplary flow of designing 1st order lead-lag filter and it's impact on PLL characteristics, so the things seem to be a little bit brighter now than they were.

Michael

Hi Michael,

Since you got LTspice, working on actual simulated circuits will be easier though I am not an expert in using it. I knew of it about one year ago.
For instance, there is also a friendly Yahoo group for it with a lot of works/examples/libs (in the group files) done through many years and a webpage indexing all of them. Obviously you will find there many links for tutorials even of video type.
**broken link removed**

About PLL, I will look in my archive and find out how to prepare for you a complete example (using CD4046 as the main IC) even if it will be for AM demodulation. As I remember I studied/simulated the basic blocks of the PLL in the s domain as well.

I will post my work (LTspice files) here though it is about a novel analogue demodulator (for its simplicity and reliability in demodulating DSB-SC so it can be fully integrated as well while it is not full digital). When I designed it, around 1979, it was a very interesting method but I kept it for my private secure links (in the 80’s) since in this period of time, there were no commercial receivers for DSB-SC system. Now, it may interest a very few amateurs who still find some applications for AM DSB-SC signals (when simplicity and efficiency are important).

Note: My internet connection (ADSL) doesn’t provide me lately continuous service as it was always the case. I doubt there is a fault somewhere; modem, cables or filter. So, I can't be sure when I can be online, before repairing/replacing the faulty part.

Kerim