+ Post New Thread
Results 1 to 2 of 2
- 22nd November 2011, 11:30 #1
- Join Date
- Dec 2010
- 9 / 9
comparision of TTL ,Cmos,ECL
can anyone compare and prioritise CMOS,TTL AND ECL with respect to Power Area & Speed...."A Friend in need
A Friend indeed :)"
- 22nd November 2011, 11:30
22nd November 2011, 12:06 #2
- Join Date
- Apr 2008
- villingen (Germany) / Bangalore
- 2144 / 2144
- Blog Entries
Re: comparision of TTL ,Cmos,ECL
ECL is fastest among the three because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the
storage time is eliminated.
The digital logic family which has the lowest propagation delay time is ECL (Lowest propagation delay time is possible in ECL because the transistors are used in
difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated).
Non-saturated Logic: In Non-saturated Logic, the transistors are not driven into saturation.
(i) Schottky TTL
(ii) Emitter Coupled Logic (ECL)
---------- Post added at 17:36 ---------- Previous post was at 17:29 ----------
Characteristics of CMOS logic:
1. Dissipates low power: The power dissipation is dependent on the power supply voltage, frequency, output load, and input rise time. At 1 MHz and 50 pF load, the power dissipation is typically 10 nW per gate.
2. Short propagation delays: Depending on the power supply, the propagation delays are usually around 25 nS to 50 nS.
3. Rise and fall times are controlled: The rise and falls are usually ramps instead of step functions, and they are 20 - 40% longer than the propagation delays.
4. Noise immunity approaches 50% or 45% of the full logic swing.
5. Levels of the logic signal will be essentially equal to the power supplied since the input impedance is so high.
Characteristics of TTL logic:
1. Power dissipation is usually 10 mW per gate.
2. Propagation delays are 10 nS when driving a 15 pF/400 ohm load.
3. Voltage levels range from 0 to Vcc where Vcc is typically 4.75V - 5.25V. Voltage range 0V - 0.8V creates logic level 0. Voltage range 2V - Vcc creates logic level 1.
CMOS compared to TTL:
1. CMOS components are typically more expensive that TTL equivalents. However, CMOS technology is usually less expensive on a system level due to CMOS chips being smaller and requiring less regulation.
3. CMOS circuits do not draw as much power as TTL circuits while at rest. However, CMOS power consumption increases faster with higher clock speeds than TTL does. Lower current draw requires less power supply distribution, therefore causing a simpler and cheaper design.
4. Due to longer rise and fall times, the transmission of digital signals become simpler and less expensive with CMOS chips.
5. CMOS components are more susceptible to damage from electrostatic discharge than TTL compenents.
" It is so simple to be happy,
but it is so difficult to be simple"
1 members found this post helpful.