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veriloga problem met in hspiceD simulation

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istyle

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i have a circuit constucted by veriloga symbols and mosfet.
When i simulate it in hspiceD simulator , the system prompt
"Netlist Error: Formatter method nlIncludeVerilogaFile not defined."
"Netlister: There were errors, no netlist was produced."
...uncuccessful.

What should i do to solve the problem? Hope for your helps! Thanks a lot!!

---------- Post added at 04:56 ---------- Previous post was at 04:07 ----------

i just find nlIncludeVerilogaFile is a skill function, but i don't know how to use this function to solve the problem above?
 

istyle said:
i just find nlIncludeVerilogaFile is a skill function, but i don't know how to use this function to solve the problem above?
Click to expand...

I'd try and type nlIncludeVerilogaFile("yourVerilogAfilename") into the CIW, before netlisting, of course.
 

erikl said:
I'd try and type nlIncludeVerilogaFile("yourVerilogAfilename") into the CIW, before netlisting, of course.
Click to expand...

I don't know exactly how to set the parameters. I have tryed to type in "nlIncludeVerilogaFile(hspiceD verilogafilename t_master)" in the CIW, but system replies "*Error* - eval : unbound variable - hspiceD".
 

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