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There are times when you NEED to use mixed compilation.
For example, you may find a core that it's written in one language, while your project is done in another language.
If, for example, you have a nice *free* open-source PCI core written in Verilog, but you design in VHDL, and VHDL PCI cores cost like 5000$ (which, for example, are only available as commercially), I think the initial question would need some considerations Well, this could be anything, not specificly PCI core!
Xilinx page specify that ISE support mixed language synthesis with Simplify Pro and XST. I don't think that ISE alone support synthesis of mixed languages, but it most probably support projects with mixed sources.
Yes friend ISE allow to mix several languages ,Sometimes is very necessary . verilog+ VHDL + HDL no problem! Ise is a nice enviroment !
Is a necessity in this evolving world !
If you are confused, you still can use XST to compile both VHDL and Verilog into NGC files separately. Then you can build, map, place & route starting from NGC files.
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Well, this could be anything, not specificly PCI core!