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CMOS OP-Amp - Where is the noise limit?

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hagen

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Dear Analog IC Design Gurus,

not being a specialist (or even a bloody beginner in Chip design) I am
trapped by the question for the smallest thermal noise possible in
CMOS- technology.

For a project I am looking for a CMOS- Opamp, 0,35um technology, 3,3V
supply, rail-to-rail (input and output) and a noise figure of better than
1,8nV/SQR(Hz).

It has to be CMOS, it has to be 0,35um tech - due to die- sharing.

Would there be a real chance to beat 1,8nV per Opamp? Could noise
versus ft be adjustable?

I am really lost - so any help and advice would be vera much apreciated.

hagen
 

Just curious, which spectrum range are you working on? To concern noise issue, first stage is the most important.
 

The first stage is biger(include W and L)
and the tail current is larger too
 

Noise mostly depends upon the first amplifying stage, that is differential pair and active load.

To minimize noise, transistors should be as big as possible (this reduces 1/f noise) with gm as large as possible (this reduces thermal noise). Obviously, current consumption appears in your tradeoffs.

See any book on analog design (Sansen and Laker, Martin, Holdberg, Gray and Meyer, Razavi)
 

The spectrum range will be up to 100 KHz.

By the way, the how is of less importance - it is the question what is
achieveable under the given conditions. Reason for this is to set up
some realistic specifications for a bunch of external design gurus.

So far all your input is really apreciatedjavascript:emoticon(':D')

hagen
 

...also remember, PMOS diff pair will give better noise performance...

Regards,
@ir@ce
 

Helo Hagen,
Use the input transistors aspect ration larger and load transistor aspect ratio smaller, to achive the less input referred noise.
Please go through with the Dr.Raazvi book, he has expalin the noise concept at circuit level very clearly.

Suraj
 

Looks like your band of interest includes DC. To effectively reduce 1/f noise in your case, you may consider chopper-stabilization technique.
 

Use any ic like 7650S (ie. chopper type). It will solve your problem
 

hi all,

Noise mostly depends upon the first amplifying stage, that is differential pair and active load.

To minimize noise, transistors should be as big as possible (this reduces 1/f noise) with gm as

large as possible (this reduces thermal noise). Obviously, current consumption appears in your tradeoffs.

please refertext book on analog design (Sansen and Laker, Martin, Holdberg, Gray and Meyer, Razavi).

thanx.
 

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