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what is crossover pin in PR?

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irun2

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In the clock synthesis phase, SOC Encounter complains like below:
** Pin mcu_otp/pwd0/clk_src_gate/U1/Y is a crossover pin between Clock OSCX_CLK and OSC_CLK
--- Overlapped subtree rooted at mcu_otp/pwd0/clk_gen/clk_gate/U19/Y:
Excluded Term top/clk_gen/clk_gate/U15/B1 is found in clock OSC_CLK but NOT in clock OSCX_CLK.
.....
**ERROR: (SOCCK-211): CTS was unable to trace clock OSC_CLK.

Waht is crossover pin after all? Does the rtl need to be re-coded?
 

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