Illegal sequential statement (VHDL)

I have a bit of a problem here. I'm a student of Computer Technology and Informatics in a greek university in athens, I have some kind of 'major project' in vhdl design, but there is an issue I can't find any solution about.

We are asked to design an arithmetic circuit which takes four 16x8bit arrays of unsigned numbers as inputs, two of them saved in two SSRAM memories. So for those last two the main model of an SSRAM 16x8bit memory is required, I made it, it's fine, and then two separate entities with their structural behavior based on the SSRAM model for the two arrays, done that, it's fine too. But, I need the data of the two arrays in memory to be 'extracted' in the main architecture of my arithmetic circuit. To show you parts of the code now:

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-- the main model for the sram
entity SSRAM_16x8 is
port (clk : in std_logic;
write : in std_logic; -- a kind of enable switch if you want to write new data in an address of the sram
addr : in std_logic_vector(3 downto 0); -- the address
din : in unsigned(7 downto 0); -- the data
dout : out unsigned(7 downto 0));
end entity SSRAM_16x8;

--the structure of one of the arrays in memory
entity SSRAM_16x8_A is
port(a_b : in std_logic; -- kind of switch again between the two arrays. when write='1', you select a_b='0' or '1'
-- to point to which one of the SRAMs to write the new data
write : in std_logic;
clk : in std_logic;
addr : in std_logic_vector(3 downto 0);
din : in unsigned(7 downto 0);
douta : out unsigned(7 downto 0));
end entity SSRAM_16x8_A;

architecture struct of SSRAM_16x8_A is
signal wr : std_logic;
begin
wr<='1' when write='1' and a_b='0';
SRAM_A: entity work.SSRAM_16x8(beh)
port map(clk,wr,addr,din,douta); -- as you see the port map goes accordingly to the port
-- of the SSRAM_16x8 entity
end architecture struct;
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I believe there is no point in giving you the exact behavior of the main SSRAM model or any other because I don't think the problem lyes there. So, we have those models, so far so good. But, I have to use the two structures in the main project and my code goes like this at this point

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SRAM : process (write) is -- I made it sensitive to 'write' signal here because is the part to use the structure
-- only to write in memory, not to read from it.
begin
if write'event and write='1' then
SRAM_A: entity work.SSRAM_16x8_A(struct)
port map(a_b, write, clk, addr, din, out_a); -- as you can see the port map goes according to the
-- port of the SSRAM_16x8_A entity
SRAM_B: entity work.SSRAM_16x8_B(struct)
port map(a_b, write, clk, addr, din, out_b); -- same here, but now this is for the second SSRAM
end if;
end process SRAM;
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Well, my libraries are fine, my signal declarations too, my packages for some extra types too. Why does it keep giving me this?

vcom -work work -2002 -explicit {C:\project-csd-sep2011-b\SSRAM_16x8.vhd}
Model Technology ModelSim PE Student Edition vcom 10.0c Compiler 2011.07 Jul 22 2011
-- Loading package STANDARD
-- Loading package TEXTIO
-- Loading package std_logic_1164
-- Loading package NUMERIC_STD
-- Compiling package array_types
-- Loading package array_types
-- Compiling entity SSRAM_16x8
-- Compiling architecture beh of SSRAM_16x8
-- Compiling entity SSRAM_16x8_A
-- Compiling architecture struct of SSRAM_16x8_A
-- Loading entity SSRAM_16x8
-- Compiling entity SSRAM_16x8_B
-- Compiling architecture struct of SSRAM_16x8_B
-- Compiling entity Arithmetic_Circuit_B
-- Compiling architecture beh of Arithmetic_Circuit_B
-- Loading entity SSRAM_16x8_A
** Error: C:\project-csd-sep2011-b\SSRAM_16x8.vhd(134): Illegal sequential statement.
-- Loading entity SSRAM_16x8_B
** Error: C:\project-csd-sep2011-b\SSRAM_16x8.vhd(136): Illegal sequential statement.
** Error: C:\project-csd-sep2011-b\SSRAM_16x8.vhd(149): Illegal sequential statement.
** Error: C:\project-csd-sep2011-b\SSRAM_16x8.vhd(151): Illegal sequential statement.
** Error: C:\project-csd-sep2011-b\SSRAM_16x8.vhd(162): VHDL Compiler exiting

As you can see ALL the previous entities and architectures are compiled succesfully, when it comes to load the entities SSRAM_16x8_A and SSRAM_16x8_B (where there is the blue text in the code) I get those errors.

Please give me some help, or even pm me for the whole code if you need it. I'd like to solve this without asking for help from my professor. And I have loads of work to do with the test benches after this. Thank you in advance!

you cannot instantiate an entity inside a process. hardware doesnt work like that.

Instead of thinking of entities like C functions, think of them more like components on a circuit board. They are not created as and when you need them, they are there all the time, running all the time, responding to inputs.

Entities are instantiated outside of processes and processes update signals that connect to the entities.

The problem is that you've put in two entities into one file.. and are trying to instantiate one entity inside the other one. I think what you wanna do is declare one of them SSRAM_16x8 as a component in the SSRAM_16x8_A entity and then just port map them..

SSRAM_A: SSRAM_16x8
port map(clk,wr,addr,din,douta);

or use a configuration to bind entities in ur project.

2 entities in one file is not the problem. It should never be a problem as long as they are reference correctly - and you DONT need to use components.

The problem is instantiating entities inside a process.

TrickyDicky you were absolutely right. Now I can understand better what they all mean when they say about vhdl "don't think as a programmer but as an electronic curcuit designer". Thank you very much! I did a major progress today thanks to you! I only hope now the logical parts of my project to be correct.

Really really thank you ,