medya
Newbie level 3
requirments for design of Pipelined adc
Hi ,I’m designing a 14bit 100MS/s Pipelined ADC (1.8v 0.18um CMOS) and need to an OTA(for front end T/H and MDAC of first stage) with this minimum requirements DC gain:96dB and Fugbw:662MHz with CL=10pf(CS =6.6pf)my main question is that how much margin must be considered in OTA design(how much DC gain and unity gain band width??) due to other non-idealities???I need to know SR and PM for this design too.
Note that the ADC must be reach the ENOB around 10-13bit and SFDR>85dB.some of references assuming Tsettling to be 2/3(kTs) and slew rate=1/3(kTs), k=50%.
Hi ,I’m designing a 14bit 100MS/s Pipelined ADC (1.8v 0.18um CMOS) and need to an OTA(for front end T/H and MDAC of first stage) with this minimum requirements DC gain:96dB and Fugbw:662MHz with CL=10pf(CS =6.6pf)my main question is that how much margin must be considered in OTA design(how much DC gain and unity gain band width??) due to other non-idealities???I need to know SR and PM for this design too.
Note that the ADC must be reach the ENOB around 10-13bit and SFDR>85dB.some of references assuming Tsettling to be 2/3(kTs) and slew rate=1/3(kTs), k=50%.
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