ERROR:Pack:679 while mapping in Xilinx ISE 9.1

Hey guys, I suffered some problem while mapping in Xilinx ISE 9.1. And I find there are several similar posts about this problem in Edaboard ,but not any answer.I found some resolutions in Xilinx's website, like

"10.1 Floorplanner - "ERRORack:679 - Unable to obey design constraints." (No DRC check on Virtex FF clock)" **broken link removed**

"ERRORack​:679 - Unable to obey design constraint​s using ISE 10.1.03."
ERRORack:679 - Unable to obey design constraints... - Xilinx User Community Forums

"9.2i MAP - Master Answer Record for debugging "Pack:679" and "Pack:2811" failures"
**broken link removed**

"ISE 8.2.3i MAP ERRORack​:679 - Unable to obey design constraint​s"
ISE 8.2.3i MAP ERRORack:679 - Unable to obey des... - Xilinx User Community Forums

"6.1i Virtex-II MAP - "ERRORack:679 - Unable to obey design constraints..."
**broken link removed**

And the resolution about the problem 's not the same, like set a new variable or update to a latest one ,etc.
I mapped the FFT256 module in Xilinx ISE 9.1 using Virtex 4 and Virtex 5 devices respectively,and the error suffered only in Virtex5 device .The project specification's like:

Project:
Project Name: FFT256
Project Path: F:\fft_256\route3\FFT256
Top Level Source Type: EDIF

Device:
Device Family: Virtex5
Device: xc5vlx30
Package: ff324
Speed: -1

Synthesis Tool: XST (VHDL/Verilog)
Simulator: ISE Simulator (VHDL/Verilog)
Preferred Language: Verilog

Enhanced Design Summary: enabled
Message Filtering: disabled
Display Incremental Messages: disabled

EDIF Sources:
F:/fft_256/rev_4/fft256.edf copy to Project

Does the situation infer ISE 9.1 not support for Virtex5 device ?How to resolve this message? Anyone suffer the same problem, please help! Also ,if there were some conclusion on this message in different ISE edition, it would be better ,thanks.