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CMOS Inverter design Issue

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RONI VINCENT

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>I am designing an inverter in 130nm tecnology.
>when i am doing transient simulation i am getting voltage spikes.
>VDD=1.2v, Input VPULSE= 1.2v, but spike around 0.2v( Output 1.4volts)
>my doubt is,, we are applying a 1.2 Voltage source but getting a 1.4v output...
>How does it happen ??? where does this extra energy come from???
>even the DC characteristic is perfect.
 

keith1200rs said:
It sounds like feedthrough due to gate-drain capacitance. It is fairly normal.

Keith
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thank u for your kind reply.. . As i am just beginning through the basics, Can you help me in getting a detailed explanation of the phenomenon if time permits you...

regards
RONI VINCENT
 

If you start with the input low and output high then take the input high, you would expect the output to go low. Before it gets chance to do this, the small capacitance from the gate to drain of the transistors couples to fast rising edge of the input pulse to the output, adding to the output voltage which is already high. When the transistors start to switch they will soon pull the output back down. If you add a small output (load) capacitance the effect will reduce considerably. The next gates loading the output will do that to some extent.

Keith
 
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