what is `celldefine in Verilog

Hi,

could anyone explain about `celldefine?

What is it? and where it is used?

Thanks!

this is mainly meant for back annotation.

The `celldefine and`endcelldefinecompiler directives tagmodule instances as cell instances. More than one pair of `celldefineand`endcelldefinecompiler directives can appear in a single source description.Certain PLI access routines use cells for applications such asdelay calculation. Verilog-XL does not mark macro modules(which it expands inline) as cell instances. Refer to the PLI 1.0 Reference and User Guideand theVPI Reference and User Guidefor more information about access routines thatrecognize cells and the use of cells in delay calculation.
Note:You do not need to apply these compiler directives tocells extracted from libraries, because Verilog-XLautomatically tags modules as cells unless you invoke it withthe command-line plus option+nolibcell

The directives ‘celldefine and ‘endcelldefine tag modules as cell modules.
This directive is used for standard cells, io cells, memory ip blocks modules outside the module definition. This modules contains logic primitives and timing section (specify) that is used for timing analysis.

Just to add to the above comments and what I understood by 'celldefine: I came across this 'celldefine directive in the libraries used by tmax for running ATPG.

'celldefine defines a module as a cell module, which means, if these modules have any instances of some other sub-modules, then these sub-modules will be masked. For running ATPG, when I read the cell modules, the faults due to sub-modules were ignored.

Everytime I searched for the meaning of 'celldefine, I was expecting an asnwer of this kind.