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A problem related to calibre PEX

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superleaf

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The layout have passed the DRC and LVS in Cadence simulation platform,and then I made a calibre PEX simulation to extract prasitic resistance and capacitance,in the extracted schematic,i found something weird,the number of MOS is more than the mos in the original schematic,for example,if the finger of the MOS is 4,the number of the this kind of MOS is 1 in the original schematic,then in the extracted schematic,the number of this kind of MOS become 4*1=4,and current Id which run through the MOS also change after extraction!so strange!!I don't know what is the problem is?Anyone who have encountered the problem like this?Appreciate your help!
 

I'd guess your extraction rules file doesn't handle C@dence' finger / multiplicity parameters correctly.
 

erikl is correct several foundry rulesets for Calibre neglect the difference between m and nf, the devices undergo parallel reduction and are compared as such. While this should not compromise the extracted netlist accuracy it can easily create mismatch between schematic and post-layout simulations even when parasitic are not to blame.

Using DSPF annotation (if your simulator can handle it) let's you discriminate between device extraction and interconnect extraction effects by annotating them separately.

There are several options to improve on this, in particular in recent versions of calibre one can run gate-level extraction using p-cells as gates which completely preserves foundry model accuracy.
 

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