ASIC_int
Advanced Member level 4
Hi
What are all the reasons to do gate level simulation? Is it only to see if gate level circuit is functionally operating or not because of the reason though the RTL verification shows the RTL to be working functionally but the gate level may not work functionally because of error in synthesis?
Regards
What are all the reasons to do gate level simulation? Is it only to see if gate level circuit is functionally operating or not because of the reason though the RTL verification shows the RTL to be working functionally but the gate level may not work functionally because of error in synthesis?
Regards