justin
Junior Member level 2
cadence edif import
I design a mixed circuit, and I want to simulate it through s*nopsys design analyzer and cadence. I design digital part in verilog, and then synthesize it in DA, and save it as edif file. When I want to import it into cadence, I failed. I in fact want to simulate in hspice.How can I do? Is the method possible?
When I save it as verilog file after synthesized, failed again.
I just want to simulate in this form, because the main part is in analog.
Can spectre perform this? How to do?
thanks
Best Regards
I design a mixed circuit, and I want to simulate it through s*nopsys design analyzer and cadence. I design digital part in verilog, and then synthesize it in DA, and save it as edif file. When I want to import it into cadence, I failed. I in fact want to simulate in hspice.How can I do? Is the method possible?
When I save it as verilog file after synthesized, failed again.
I just want to simulate in this form, because the main part is in analog.
Can spectre perform this? How to do?
thanks
Best Regards