can anybody tell me what is wrong with this code?

Hi,

My input clock is of period 100 with 50% duty cylce. I have two T-Flipflops. Each has outputs Q1 and Q2 respectively.I would like to add a delay of 8.144ns to Q1 and 10.386ns to Q2.
so that Q3<=Q1+8.144ns;
and Q4<=Q2+10.386ns;

and I would like to generata an enable so that en<=Q3 xor Q4;

I managed to write the code and it is being simulated but with small error.
The enable is becoming high at certain intervals and ignoring next 2 levels of unequal outputs of Q3 and Q4. Then for another 2 levels it is 1.
Please check and correct the code ASAP. Pleaseeeeeeeee

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity controlckt is
port(clk: in std_logic;
en : out std_logic := '0');
end controlckt;

architecture arch1 of controlckt is
signal Q1,Q2,Q3,Q4 : std_logic := '0';
signal t: std_logic := '1';

begin
process(clk)
BEGIN

if (clk = '1' and clk'event) then
Q1<= (t and (not Q1)) or ((not t) and Q1);
end if;

if (clk = '1' and clk'event) then
Q2<= (t and (not Q2)) or ((not t) and Q2);
end if;

end process;

process
begin
wait for 8.144 ns; --dmin delay
Q3 <= Q2;
wait for 10.836 ns; --dmax delay
Q4 <= Q1;

en<= Q3 xor Q4;

end process;
end arch1;

Thankyou.

you cannot synthesise this as wait statemenets are generally not synthesisable. They are only suitable for simulation.

They are very presice delays to want. why do you ned them?

from another article, it looks like he is trying to do "wave pipelining" which is a type of pipelining that doesn't use registers. It relies on careful design methods to balance the delays to each stage. This makes it significantly more difficult to design and analyze than traditional pipelining.

I would expect that your synthesis tools would need to be aware of wave pipelining, or that you'd have to model it in verilog, but actually do the design in VLSI or a FPGA layout editor. There is a very good chance that the verilog won't be synthesizable (will ignore delays).

as for the code, i suspect the wait for -- wait for is the issue. more likely, you want to define Q3 as Q2 after 8.144ns, and Q4 as Q1 after 10.836ns.
right now, the code literally does wait for 8.144ns, set Q3 to Q2. wait 10.836ns after these 8.144ns, set Q4 to Q1.

**broken link removed**
This describes how to model the delays using x <= y after 1ns; as well as x <= transport y after 1ns; Again, just modeling the delays. The tools would need to know what to do with these, or you'd have to provide a manual solution.

There is a very good chance that the verilog won't be synthesizable (will ignore delays).

Click to expand...

You shouldn't give room for speculations. It's pretty clear that timed wait for doesn't work in synthesis, even if the code compiles without errors. .Asynchronous timing circuits, e.g. involving logic cell delays can be designed in FPGA, but are effectively unsupported by the design tools. You should also consider, that logic cell and routing delays are affected by PVT (process, voltage, temperature) variation, a variation factor of e.g. 1:2 is quite normal.

yes,

You are correct. i am trying to implement wave-pipelining by considering precise delays. But I am getting problem with the equalization of path delays. How to do that? I am very new to vhdl. I dont know how to make such precise delays to be synthesizable.

i am using xilinx spartan3 for synthesis and implementation.

Could you please help me in letting me know how to model the design using FPGA Editor?

Kindly help me out.

You can simulate design concepts like wave pipelining in a full featured simulator, e.g Modelsim. Unfortunately I don't know, if the integrated Xilinx simulation tools will allow it.

The important point is however, that Xilinx XST synthesis tool (or any integrated tool from another major FPGA vendor) isn't prepared to support wave pipelining or similar asynchronous concepts. I also doubt, if the expectable delay variation in FPGA will ever allow to implement the concept reliably.

Indeed. If you are trying this on an FPGA, you would have to basically do what I said -- use the HDL for simulation and logic debugging only. Then you'd have to manually design, place, and route the logic. Then you'd have to run post-implementation worst-case sims to make sure the design works over PVT (and logically). The same would go for an ASIC, but an ASIC at least gives you more control over the routes.

it would be more common in an FPGA to just generate a faster clock, and then do all of the logic in the faster clock domain.