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considerations for routing clk net in mixed signal layout..

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bhagyasree

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what factors should be considered while routing clk net in mixed signal ic layout???


Thanks
 

If you can afford it, route clk & clk_b in parallel. So the influence on crossing sensitive signal lines (charge injection during clock edges) can be compensated (not totally, but to a good part). And you always have both phases available ;-) .
 

Thanks for your reply.
and can the clk net cross any analog signal routing?

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bhagyasree said:
... can the clk net cross any analog signal routing?
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You probably can't avoid it; but by crossing both phases (with their min. spacing) you can minimize its influence. I've realized this successfully for a CMOS pixel array.
 

pay attention also not to route signal path close/parallel to clock path for long distances, to avoid clock feedthrough due to the parasitic capacitance between the two lines.
 

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