Over-optimistic ADC SNR results

Hello guys,

I am designing a 6bit / 1.7Ghz Flash ADC.

To get the SFDR / SNR ect, I use the spectrum function with rectangle window. I am using coherent sampling and I strobe the transient data at the clock frequency. I also run a DFT and crosschecked that the function works as it is supposed to.

The problem is that I am getting over-optimistic results for my circuit.

Here is a DFT with 64bins


And one with 4096 points


I undestand why SFDR increases and SNR decreases varying the DFT points, but the values for SNR /SINAD/ENOB seems over-optimistic

I run a simulation with an Ideal 8bit ADC (verilog) and got the following results proving that the spectrum function works well.

64 points


4096 points


So why am I getting this results?
Should I increase the resolution (reltol ect)?
Define a smaller maxstep for the transient?
Or should I just run my sims with montecarlo so the offset are taken in account?

*Can someone change the title to "Over-optimistic ADC SNR results"?

I did a monte carlo sim (one run) and got the following.


SINAD / ENOB seems more realistic.. SNR is still very high.

What you guys do when simulating an ADC / DAC? Do you run a simple transient, or do you run montecarlo?