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help me with verilog code

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ashishk

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Hi,

I am a verification guy and want to know if following verilog codes are valid or not:

1) always @( a & b)
2) always @(a || b)
3) always @(a && b)
4) always @(a | b)

Thanks
 

One clarification. I want to know if in sensitivity list we can do '&' and '|' operation? And when it will get triggered.
 

Hi Ashishk

you can use logical statements in sensitivity list. Sometimes it uses for combinational circuits, in which all of the inputs have the same role. in the other word, it must be triggered if one of it's input changes. In this case we use or between signals in sensitivity list: always @ (a or b or c)
I have not seen using of "and" in any case.
but in sequential circuits, edge variations of signals are important.
in synchronous circuit, there is one signal (clock) in sensitivity list:
always @ (posedge clock)
always @ (negedge clock)
but in asynchronous circuits, we have more than one signal in sensitivity list:
always @ (posede clock or negede reset)
always @ (posedge clock1 or posedge clock2 )
 

just do:
always @(a and b)
always @(a or b)
or use always_comb block in system verilog.
 

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