jtag problem (many devices in the chain)

Good afternoon everyone!
I have a problem with jtag. My gear consists of up to 32 cards, each FPGA and the configuration ROM. All devices connected to jtag. Tms and tck signals pass through the buffer. . Buffer is designed so that each of its output is connected to 4 board (8 jtag devices). Up to 16 cards programmed (written to ROM) is not the first attempt. Most boards will not work (not recorded ROM).


does not depend on the frequency of TCK

how to solve the problem?

Hello Treqer,

We met before on this thread. https://www.edaboard.com/threads/208797/
Sorry you are having troubles. THe design is not entirely clear to me, but buffering signals introduces a host of problems. Buffering/Driving any signal (jtag or functional) over a long distance and having multiple end-points can introduce ringing/overshoot/undershoot. Buffering JTAG signals at the board/system level is an older approach and for the most part is in disfavor in modern designs based on the skew it introduces and the impact on timing margins.
So what to do?
Best to start with analyzing the signals with a scope at each point. Are the signals clean? Have you invested in a good quality 1149.1/JTAG board level tool or are you using the FPGA based tools? The former provides you with diagnostics when things go wrong and the latter does not.
It's probably too late now as you have already designed your system. But for next time consider using a dedicated JTAG mux such as the Scan Ring Linker

The engineers here have a good handle on the issues with system level JTAG routing.

Regards,
Cindy

Thank you for your reply. I can not understand why no effect lowering of CLK. To my knowledge, information, passing along the chain are given by one edge, and accepted by another. With such a construction, delay CLK to few nanoseconds should not be affected data transfer along the chain.

You are correct, the rising edge of TCK captures TMS and TDI and the falling edge of TCK, TDO is valid.
Signal integrity and all transmission line theory is based on the slew rate of the drivers. That is, DV/DT, the change of voltage over the change in time. So even with a very slow TCK, a fast rising or falling digital signal can cause undesirable overshoot/undershoot and ringing. It's the speed of the low to high or high to low that matters, not the TCK frequency.
Especially when driving multiple endpoints (many TCK inputs) over long distances. Each IC TCK and TMS input is a load, capacitance and a small electrical 'stub' is created by the trace/pin and package along this long transmission path. If you simulate it with hyperlynx or other SI package you would see the effects. And that is, with a controlled impedance signal, say 50ohms. You dont mention layout, but that would be another factor and another thing to look at if you signals look horrible with the scope. Your JTAG signals need to have a ground reference under them, just like any other signal. This creates the return current path. Make sure care is given during layout.
First step, start getting pictures with a scope of the JTAG signals.

Best Regards,
Cindy

Thanks. As the buffer used xilinx cpld 95144. On the oscilloscope output signals cpld not terrible, but look at the inputs TCK impossible.