gonewithstone
Newbie level 5
In Xilinx Spartan6 FPGA, instantial two PLLs, use output clock as PLL feed back in clock , one for clock multiple(25MHz in, 75MHz Out), another for clock division(125MHz in, 62.5MHz).
The test result shows the two PLL can PLL lock, the clock division can generate 62.5MHz clock, but clock multiple cann't generate 75MHz clock, only has 25MHz clock out!
Anyone knows why the clock multiple cann't work?
The test result shows the two PLL can PLL lock, the clock division can generate 62.5MHz clock, but clock multiple cann't generate 75MHz clock, only has 25MHz clock out!
Anyone knows why the clock multiple cann't work?