how to insert the design of the blackbox in SOC Encounter?

Hi all,

I am a bit new to SOC Encounter. In my design, there are several blackboxes which their .LEF, .LIB, .GDS and .DEF files are available. How and at which stage should I insert their .DEF (or whatever else) files to finalize the design?

Thanks in advance,
Nasim

When you do your design, instantiate your black boxes in your verilog file. If there is behavior model for a black box, use it in your simulation. In layout, layout tools only care about the LEF and LIB file. After you do the APR, merge the gds file of the block boxes with standard cells and IO to spit out the gds for the whole chip.

hello.. can you help on this.... I have a similar problem i think..


I have created a memory design (in cadence virtuoso). I want to attach this memory with a auto generated layout - a microprocessor (generated using soc Encounter).

the plan i have in mind is..
create a blackbox LEF Macro and a timing model (liberty file) for the memory design. The LEF macro defines the physical boundary and pins of the memory. I can then import the LEF and lib file into SoC Encounter along with the netlist for the micro and run P&R. This allows to create an integrated layout and verify timing between the micro and the memory

Can anyone tell me how to do this?
1. how to create a black box in soc encounter? what do i need for that? how to create .lef and .lib files for my memory design??
any suggestions/ideas are welcome..
a task flow or a design flow of what i have to do .. would be really helpful!!