pawangupta
Junior Member level 1
Hi all,
I want to write a configurable verilog code of case statement....please help me, if any idea...
Example_1:
In this simple example, i know how many case expressions may exist in my case loop...4:
parameter COUNT_WIDTH = 4
case (COUNT_WIDTH)
4'b0001: something;
4'b0010: something;
4'b0100: something;
4'b1000: something;
default: something;
endcase
But at latter time, user defined COUNT_WIDTH = 15, how can i write this configurable requirement in verilog HDL so that i need not to modify my RTL when user requirements changes.
CONFIGURABLE CASE LOOP ?????
I want to write a configurable verilog code of case statement....please help me, if any idea...
Example_1:
In this simple example, i know how many case expressions may exist in my case loop...4:
parameter COUNT_WIDTH = 4
case (COUNT_WIDTH)
4'b0001: something;
4'b0010: something;
4'b0100: something;
4'b1000: something;
default: something;
endcase
But at latter time, user defined COUNT_WIDTH = 15, how can i write this configurable requirement in verilog HDL so that i need not to modify my RTL when user requirements changes.
CONFIGURABLE CASE LOOP ?????