Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Need help with my Delay Locked Loop (DLL) design.

Status
Not open for further replies.
S

spec07

Junior Member level 2
Joined
Aug 18, 2010
Messages
22
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,414
Hi,

I need help with my DLL design which consist of a phase detector, charge pump loop filter and a voltage control delay line(VCDL). The input of the phase detector is fed by 2 clocks (clock reference and output clock with is a feedback from the output of the VCDL. The problem I am facing now is that I am unable to lock the reference clk and output clk despite running the simulation for 300us. I am simulating at 1Mhz for the clock pulses.

Any help and advice would be appreciated.

Thank you.
 

Maybe you should upload your design, let's check what's wrong.
 

Please have stability analysis before. Does it have enough phase margin?
 

What kind of phase margin are you referring to? Will take screen shot of the schematics and upload asap. Thanks for the prompt replies.
 

What is the number of delay stages for the VCDL required for the design if i were to use a current starved inverter? Which means how many current starved inverter I should have? For the 2 input clocks, clk_in which is input to the VCDL and clk_ref which is input to the phase detector, should I set a delay between them?
 
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top