Vary power supply to line in verilog

I designed a unit for cache. I have put the individual sets in cache as variable reg in verilog. I need to put the lines in standby mode to save power. based on the logic for address translation, lines are selectively enabled. How to achieve this in verilog?

Hi,

If I understand it correct you designed a cache with multiple cache lines.
Each cache line will be a set of register after synthesis.

Now you want to put such a set of register into standby mode. In your design this would me, you need to disable the clock to this register.
So you need to add a clock gate.

In the end you will have for every cache line an individual clock, which can be enabled or disabled depending on the algorithm of the cache.

In verilog you will have for every cache line an individual always block with an individual clock.

To design this I would use a module for one cache line and generate the whole cache with an generate statement.

Hope this helps

regards

I thank you for the reply. I tried the following to simulate a cache with eight sets.
module cl(index, r, clk, out);
input [2:0] index;
input [287:0] r;
input clk;
output out;

reg [287:0] out;
reg [2:0] temp;

always @(posedge clk)
begin
out = 0;
end


always @(negedge clk)
begin
out = r;
end

endmodule

module fa_generate(address, d, clk, l1hits);
input [31:0] address;
input [31:0] d;
output l1hits;
input clk;


reg [15:0] l1hits;
reg [2:0] temp;
wire [287:0] out[7:0];

generate
genvar j;
for (j=0; j<8; j=j+1)
begin:B1
cl c (j, d, clk, out[j]);
end
endgenerate



endmodule
I was able to synthesize the code. However I was unable to complete the Implement Design option in xilinx tool. I get the following error.
Section 1 - Errors
------------------
ERRORack:198 - NCD was not produced. All logic was removed from design. This
is usually due to having no input or output PAD connections in the design and
no nets or symbols marked as 'SAVE'. You can either add PADs or 'SAVE'
attributes to the design, or run 'map -u' to disable logic trimming in the
mapper.
I tried the -u option but the error still exists. could you please let me know what I am missing?

Hi ssubha,

I'm sorry I'm not familiar with the Xilinx FPGA design flow.
Maybe you should ask this in the FPGA forum.

regards