Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

high-gain high-BW op design

Status
Not open for further replies.
B

bambots

Newbie level 1
Joined
May 27, 2008
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,290
Hello guys!

Is there any op design/architecture such that it can have a gain of at least 65dB at 500MHz?

I am using TSMC 0.18um CMOS process. My load capacitance is about 10fF (the gate capacitance of a MOS transistor).

I tried a folded-cascode op, having a bias current of 350uA. With this, the power dissipation reaches as high as 1.5mW. But my 3-dB freq is up to 20MHz only. How can I extend the 3-dB freq to 500MHz without sacrificing more on power consumption?

I need your opinions. Thanks!
 

How can I extend the 3-dB freq to 500MHz
Click to expand...
"3-db" freq of what? Closed loop gain? But why you're asking for "gain of at least 65dB at 500MHz", in other words a GBW of 9 GHz?
 

3-db freq is -3dB freq in my guess. That's dominant pole frequency. 9GHz GBW should be mission impossible for this process.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top