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[SOLVED] verilog function in condition expression of for statement

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rainly

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Hi all,
I have a rookie question. I did the following code:

module adder #(parameter width=8)
....
for(i=0;i<log2(width);i=i+1)
.....

function integer log2;
input [31:0] value;
for(log2 = 0; value > 1; log2 = log2 + 1)
value = value >> 1;
endfunction
endmodule

I get the following error during elaboration:
Error-[V2KGEUV] Unknown or bad value for genvar
Elaboration time unknown or bad value encountered for generate for-statement condition expression.
Please make sure it is elaboration time constant.

Is it correct to use function in the condition expression of for loop?
Is it possible to solve the problem without adding another parameter for log2(width)?
Thank you in advance
 

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