ashik_na
Junior Member level 1
Dear all ,
I am designing a pipelined SAR ADC with having clock freq.>160MHz.
i want to design an input driving circuit for this high speed ADC. [ I can't give more acquisition time to charge the CDAC caps. ]
which is the most conveniet method to drive pipelined SAR ADC having clock frequency >160MHz ? using OP AMP with RC circuit or transformer coupled input stage ?
I am designing a pipelined SAR ADC with having clock freq.>160MHz.
i want to design an input driving circuit for this high speed ADC. [ I can't give more acquisition time to charge the CDAC caps. ]
which is the most conveniet method to drive pipelined SAR ADC having clock frequency >160MHz ? using OP AMP with RC circuit or transformer coupled input stage ?
