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ERROR in XILINX : Unsupported real variable

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neural84

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Hey...
I'm going to implement a neural network by FPGA.
When i running the xise file that produced by matlab in synthesis message it show 1 error and 4 warning.
I hope some body help me to solve them.
thank you.

WARNING : HDLCompilers:259 - "../IW_1_1.v" line 48 Connection to input port 'w' does not match port size.

WARNING : HDLCompilers:259 - "../IW_1_1.v" line 59 Connection to input port 'w' does not match port size.

WARNING : HDLCompilers:259 - "../IW_1_1.v" line 70 Connection to input port 'w' does not match port size.

WARNING : HDLCompilers:259 - "../Layer_2.v" line 70 Connection to input port 'n' does not match port size.

ERROR : Xst:2228 - "../Layer_1.v" line 41: Unsupported Real variable.
 

Type "real" is not synthesisable.
 

Thanks a lot for replying.

The line 41 in my code is : real b_1_out1 [0:2]; // double [3]

b_1_out1 is the out put of biases in first neuron of first layer. This output are numbers (26.131375428987404 ; -24.126840239877037 ; -22.122742581891174).
Now do you have any idea to resolve it.
I'm new in xilinx. thanks again for your help.
 

You have to use fixed point representation fort these values.
 

thank you very much.
If i fix it and had any problem can i account on your help.
 

I don't know Verilog as well as VHDL so its better to post your questions/problems here in this topic. Maybe someone else will know the answer.
 

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