[SOLVED] Synopsys design constraints

What are the constraints tool consider from SDC before and after CTS ?? If there is any good document about constraints please post me a reply??

Hi,

Your clock latency for the clock tree delay can now be calculated.

As such, you probably want to remove your estimated clock-tree insertion delay from your set_clock_latency command.

In addition, you want to tell the STA tool to calculate the delays through your clock trees; use the set_propagated_clock command for all non-ideal clocks.

Before CTS we use ideal clock for all the timing analysis & after CTS we use the implemented clock for timing analysis.

we use the command "set_propagated_clock" for using the implemented clock tree parameters.

If you need more info on this, file a Service request in Solvenet.

Thanks for reply guys.. Will there be any changes we need to do after cts in terms of uncertainty?? We will give skew b4 CTS by set_clock_uncertainty both setup and hold right.. Does set_propagated_clock will deactivate set_clock_uncertainty??

Hi, you probably still have some uncertainty in your clock at it's source, with propagated clocks you are only taking care of the uncertainty associated with the building of the clock trees. You may also want to add a small amount of uncertainty to build in some margin.

Thanks for reply JpvSoccer.. Can you tell me wat are the uncertainities associated wit building clock trees?? Am still in confusion sry.. Does tool consider uncertainty(skew) which we give b4 CTS or will it calculates and balances skew?? Is thr any document that will help to understand this please post it here..
Thanks guys...

We hate to use Prime Time to set time constraint and then create .sdc from Prime Time

Hi,

Clocks are signals in your design that have high fanout and special timing requirements.

There was a time when we could let the synthesis tool buffer clock trees, but that time has long passed.

The next design evolution was to have special tools (CTS) to build nice balanced (aka low skew between clock arrivals at flop CK pins and minimum delay) clock trees.

Now, in order to meet our timing goals, we need a special tool to build a clock trees that includes placement based (and possibly routing) results.

A clock tree is simply a buffer tree where the end points hit CK pins.

When we run synthesis, the tool creates a design that meets your target clock frequency; it builds combinatorial logic that meets the setup and hold requirements of the flip flips as a function of the clock period.

Since we now need to build our clock trees later in the design cycle (we need to build the gates before we go into placement), we need to have the synthesis tool estimate the clock arrival times at the flop CK pins.

We first tell the tool what we think the buffer-tree insertion delay will be.

Then we need to tel the tool about the different arrival times on all of the CK pins. Since the CTS tool is not perfect, you can assume that every flop in your design receives the clock at a different time. This different arrival time is related to buffer-tree structure, placement of buffer-tree cells, routing between buffers, and routing from the last buffer (leaf cell) to the clock pins of flops. These different arrival times are what we call clock tree uncertainty.

After we build a clock tree, the synthesis tool can now be used to time and fix setup and hold delays for paths that are broken due to the imperfections associated with CTS.

A typical flow is as follows:
Synthesize design using IDEAL clocks. These IDEAL nets will not have logic inserted on them by the synthesis tool. In order to get the best synthesis results, we tell the tool the predicted timing characteristics of the clock tree that will be build later in the design flow. We tell the tool how much buffer delay the tree will have and how much skew between CK pins we can expect.

After CTS, we tell the synthesis tool that the clock nets are not IDEAL. The synthesis tool can now propagate timing arcs through the clock tree and use this information to identify setup and hold problems.

Note: a good thing to do is to always assume that every CK pin will get a slightly different clock arrival time. There are no IDEAL nets in silicon...

ldhung said:

We hate to use Prime Time to set time constraint and then create .sdc from Prime Time

Click to expand...

We don't use prime time to set and write constraints...Prime time is a tool to analyze timing of a design with paths already constrained ie Static timing analysis. If paths are not constrained then prime time or any other STA tool won't analyze the paths.

---------- Post added at 16:16 ---------- Previous post was at 15:43 ----------

Thanks again JpvSoccer. Thanks for the descriptive answer. Now i understood clearly where the uncertainty matters. Thanks once again.. Will post you if i have any doubts.