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how to interpret hardware generated from vhdl code

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s3034585

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xilinx ise schematic output

hi can any one tell me how to interpret hardware generated from a vhdl code. what difference does it make when you make changes like using signals instead of variables or changing the sensitivity list. where can i get reading material on this.
Thanks
 

HI 303...HUmmm . that looks like my area code!
Listen .. it looks like you are a newbie ..in VHDL ,,It's ok ..ypu need a good book .Also i know a good way that i always advice to newbies .. Use xilinx ISE there is a schematic output block production .
When you write VHDL ,.. compile and then see the block diagram produced .. it will show all the flip flops ,registers and other logical primitives .. It's very nice ,.change this here and there and see right away
the block diagram synthetized by ISE ..
Get ISE from the XILINX web site .. it's only 5 bucks to order it!
 

A good book on that subject is A VHDL Synthesis Primer. It covers processes, etc, and how they directly convert in to gate level schematics.. I read A Verilog Synthesis Primer and it was good!

jelydonut
 

You may also try searching the internet (i.e. google) for University presentations about "synthesizable VHDL constructs". There you will see differencies between signals and variables and many other things. A post-synthesis schematic can be very helpful as stated above.
 

jelydonut said:
A good book on that subject is A VHDL Synthesis Primer.

hi, jelydonut

Can you tell us where we can find the pdf vision of the book? I hope that I can read it for improving my synthesis knowledge.

Thank you
 

Basically you need to get your hands on docs like Design for Synthesis. Also need to experiment with coding styles to see how the RTL schematic changes with the change in code.
 

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