s3034585
Full Member level 4
xilinx ise schematic output
hi can any one tell me how to interpret hardware generated from a vhdl code. what difference does it make when you make changes like using signals instead of variables or changing the sensitivity list. where can i get reading material on this.
Thanks
hi can any one tell me how to interpret hardware generated from a vhdl code. what difference does it make when you make changes like using signals instead of variables or changing the sensitivity list. where can i get reading material on this.
Thanks