Multiplication by 3 in Verilog- Unsigned or Signed

Hi there,
Recently I was trying to write a Verilog Code for Multiplication by 3.

Condition-My Input is variable-Unsigned or Signed
My Multiplier is fixed-3

So if i have -20 as input in binary my output should by -60.
and 20 as input my output should be +60.

I want to declare only one output that is product and depending on clock pulse and input my output should be latched.


I wrote the code but it's not working. 3 is just 1 shift and 1 add.

Can anyone here suggest me the code so i can proceed in right direction??


Thanks a ton.

What do you mean by not working ?

The code must be very simple. Only thing that you need to be careful about is you need to sign extend when you do 'add' with signed numbers.

This is the code. Can you tell me what's wrong in this ????


module multi (prod,bin, clk,en, res);

input [8:0] bin;
input clk, res, en;
output [10:0] prod;

reg [10:0] prod;
wire [10:0] prod_temp;
wire [10:0] temp, temp1, temp2;


always @ (posedge clk or negedge res)
begin
if (!res)
begin prod <= 0; end
else if (en)
begin prod <= temp2[10:1]; end
end

assign prod_temp = {11'b0000000000000};
assign temp= prod_temp + {bin, 2'b00};
assign temp1 = {bin[8], temp[10:1]};

assign temp2 = temp1 + {bin, 2'b00};

endmodule

---------- Post added at 22:36 ---------- Previous post was at 22:35 ----------

This is the code. Can you tell me what's wrong in this ????


module multi (prod,bin, clk,en, res);

input [8:0] bin;
input clk, res, en;
output [10:0] prod;

reg [10:0] prod;
wire [10:0] prod_temp;
wire [10:0] temp, temp1, temp2;


always @ (posedge clk or negedge res)
begin
if (!res)
begin prod <= 0; end
else if (en)
begin prod <= temp2[10:1]; end
end

assign prod_temp = {11'b0000000000000};
assign temp= prod_temp + {bin, 2'b00};
assign temp1 = {bin[8], temp[10:1]};

assign temp2 = temp1 + {bin, 2'b00};

endmodule

er.twi.fb said:

input [8:0] bin;
output [10:0] prod;

wire [10:0] prod_temp;
wire [10:0] temp, temp1, temp2;

assign temp1 = {bin[8], temp[10:1]};
assign temp2 = temp1 + {bin, 2'b00};

Click to expand...

What are you going to do if the above addition overflows ?

the first thing is the vector [10:0] being assigned something[10:1].

You might also want to just do a shift and add. You are currently doing extra shifts in the intermediate steps. while 11b is enough to hold any 9b value multiplied by 3, it is not enough to hold any 9b value multiplied by 6 (which is what you do in an intermediate step).