RC Synthesis mapper Query

Hi Guys,

I am new to RC synthesis Tool.
While doing synth -to_map, RC dumps the global estimated target slack as :
========
Cost Group 'abc1' target slack: 59 ps
Target path end-point (Pin: top/abc/abc1/dataram_rdata_lat_reg_03/d)

Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'top'.
Pin Type Fanout Load Arrival
(fF) (ps)
-------------------------------------------------------------------------------------
(clock dside_clk) <<< launch 575 F
latency
top
abc
a_ram_arrays
a_ddata_bank4/CLK
a_ddata_bank4/Q[31] (u) (P) RF1CC_1024X32M8 1 5.0
a_ram_arrays/ddataram_rdata0_o[03]
abc1/dataram_array_rdata_i[03]
dataram_rdata_lat_reg_03/d <<< unmapped_latch
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
(clock dside_clk) open
latency
uncertainty
dataram_rdata_lat_reg_03/ena borrowed
-------------------------------------------------------------------------------------
Cost Group : 'abc1' (path_group 'abc1')
Start-point : top/abc/a_ram_arrays/a_ddata_bank4/CLK
End-point : top/abc/abc1/dataram_rdata_lat_reg_03/d

(P) : Instance is preserved
(u) : Net has unmapped pin(s).

The global mapper estimates a slack for this path of 59ps.
===============


I wish to know 2 things here:
1, What does target slack means?
2, And, when RC has not done the mapping of all the instances in the design, then how does RC estimates the slack for this path?


Please help to provide your suggestions on this.

Thanks!
bharat

Hi, it appears that the ram access time is such that it eats into your cycle time.

What are the periosd of the clocks ?

What is the CLK - Q for the RAM?

It looks like the setup time for dataram_rdata_lat_reg_03 may be violated.

Should this be a multicycle path?

Do you have a report_timing -from a_ddata_bank4/CLK -to dataram_rdata_lat_reg_03/d ?

Hi jpvSoccer,

I got this path closed after mapping and optimization.

But, What i want to know is that the timing summary which has been dumped by RC is dumped before it started actual mapping (as u can see the unmapped instance "dataram_rdata_lat_reg_03/d <<< unmapped_latch" in the report dumped by RC).

I wish to know 2 things here:
1, What does target slack means which RC is reporting in log file for each cost group before doing the actual mapping ?
2, And, when RC has not done the mapping of all the instances in the design, then how does RC estimates the slack for this path?

Thanks!
bharat

Hi, what you are asking about are the types of things that make one synthesis better or worse than another; I can't talk to how RC does its thing...

We want a synthesis tool to structure the design properly and converge on the best solution in a timely fashion.

If a tool can quickly come to an initial structuring that is close to the target, then you are better off.

If a tool uses some special-sauce to guess where the timing will likely be after mapping, than we want the tool to do that.

Cost functions drive synthesis structuring and mapping; if you want less area then you select a different structure than if you want a faster design.